# Reading C:/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl
# do VGA_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap work rtl_work 
# Copying C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+C:/Users/ZXR001/Desktop/vga_01/ipcore {C:/Users/ZXR001/Desktop/vga_01/ipcore/pll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:27:46 on Mar 20,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/ZXR001/Desktop/vga_01/ipcore" C:/Users/ZXR001/Desktop/vga_01/ipcore/pll.v 
# -- Compiling module pll
# 
# Top level modules:
# 	pll
# End time: 18:27:46 on Mar 20,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/ZXR001/Desktop/vga_01/src {C:/Users/ZXR001/Desktop/vga_01/src/VGA_character.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:27:46 on Mar 20,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/ZXR001/Desktop/vga_01/src" C:/Users/ZXR001/Desktop/vga_01/src/VGA_character.v 
# -- Compiling module VGA_character
# 
# Top level modules:
# 	VGA_character
# End time: 18:27:46 on Mar 20,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/ZXR001/Desktop/vga_01/prj/db {C:/Users/ZXR001/Desktop/vga_01/prj/db/pll_altpll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:27:46 on Mar 20,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/ZXR001/Desktop/vga_01/prj/db" C:/Users/ZXR001/Desktop/vga_01/prj/db/pll_altpll.v 
# -- Compiling module pll_altpll
# 
# Top level modules:
# 	pll_altpll
# End time: 18:27:46 on Mar 20,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+C:/Users/ZXR001/Desktop/vga_01/prj/../src {C:/Users/ZXR001/Desktop/vga_01/prj/../src/tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:27:46 on Mar 20,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/ZXR001/Desktop/vga_01/prj/../src" C:/Users/ZXR001/Desktop/vga_01/prj/../src/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 18:27:46 on Mar 20,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc"  tb
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" tb 
# Start time: 18:27:47 on Mar 20,2021
# Loading work.tb
# Loading work.VGA_character
# Loading work.pll
# Loading altera_mf_ver.altpll
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading altera_mf_ver.pll_iobuf
# Loading altera_mf_ver.MF_cycloneiii_pll
# Loading altera_mf_ver.cda_m_cntr
# Loading altera_mf_ver.cda_n_cntr
# Loading altera_mf_ver.cda_scale_cntr
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.inst_VGA_01.pll_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 90000  Instance: tb.inst_VGA_01.pll_inst.altpll_component.cycloneiii_pll.pll3
add wave -position insertpoint sim:/tb/inst_VGA_01/*
restart
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.inst_VGA_01.pll_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 90000  Instance: tb.inst_VGA_01.pll_inst.altpll_component.cycloneiii_pll.pll3
run -all
do VGA_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap work rtl_work 
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+C:/Users/ZXR001/Desktop/vga_01/ipcore {C:/Users/ZXR001/Desktop/vga_01/ipcore/pll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:36:25 on Mar 20,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/ZXR001/Desktop/vga_01/ipcore" C:/Users/ZXR001/Desktop/vga_01/ipcore/pll.v 
# -- Compiling module pll
# 
# Top level modules:
# 	pll
# End time: 18:36:25 on Mar 20,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/ZXR001/Desktop/vga_01/src {C:/Users/ZXR001/Desktop/vga_01/src/VGA_character.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:36:25 on Mar 20,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/ZXR001/Desktop/vga_01/src" C:/Users/ZXR001/Desktop/vga_01/src/VGA_character.v 
# -- Compiling module VGA_character
# 
# Top level modules:
# 	VGA_character
# End time: 18:36:25 on Mar 20,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/ZXR001/Desktop/vga_01/prj/db {C:/Users/ZXR001/Desktop/vga_01/prj/db/pll_altpll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:36:25 on Mar 20,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/ZXR001/Desktop/vga_01/prj/db" C:/Users/ZXR001/Desktop/vga_01/prj/db/pll_altpll.v 
# -- Compiling module pll_altpll
# 
# Top level modules:
# 	pll_altpll
# End time: 18:36:25 on Mar 20,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+C:/Users/ZXR001/Desktop/vga_01/prj/../src {C:/Users/ZXR001/Desktop/vga_01/prj/../src/tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:36:25 on Mar 20,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/ZXR001/Desktop/vga_01/prj/../src" C:/Users/ZXR001/Desktop/vga_01/prj/../src/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 18:36:25 on Mar 20,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc"  tb
# End time: 18:36:26 on Mar 20,2021, Elapsed time: 0:08:39
# Errors: 0, Warnings: 0
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" tb 
# Start time: 18:36:26 on Mar 20,2021
# Loading work.tb
# Loading work.VGA_character
# Loading work.pll
# Loading altera_mf_ver.altpll
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading altera_mf_ver.pll_iobuf
# Loading altera_mf_ver.MF_cycloneiii_pll
# Loading altera_mf_ver.cda_m_cntr
# Loading altera_mf_ver.cda_n_cntr
# Loading altera_mf_ver.cda_scale_cntr
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.inst_VGA_01.pll_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 90000  Instance: tb.inst_VGA_01.pll_inst.altpll_component.cycloneiii_pll.pll3
add wave -position insertpoint sim:/tb/inst_VGA_01/*
restart
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.inst_VGA_01.pll_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 90000  Instance: tb.inst_VGA_01.pll_inst.altpll_component.cycloneiii_pll.pll3
do VGA_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap work rtl_work 
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+C:/Users/ZXR001/Desktop/vga_01/ipcore {C:/Users/ZXR001/Desktop/vga_01/ipcore/pll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:51:12 on Mar 20,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/ZXR001/Desktop/vga_01/ipcore" C:/Users/ZXR001/Desktop/vga_01/ipcore/pll.v 
# -- Compiling module pll
# 
# Top level modules:
# 	pll
# End time: 18:51:12 on Mar 20,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/ZXR001/Desktop/vga_01/src {C:/Users/ZXR001/Desktop/vga_01/src/VGA_character.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:51:12 on Mar 20,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/ZXR001/Desktop/vga_01/src" C:/Users/ZXR001/Desktop/vga_01/src/VGA_character.v 
# -- Compiling module VGA_character
# 
# Top level modules:
# 	VGA_character
# End time: 18:51:12 on Mar 20,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/ZXR001/Desktop/vga_01/prj/db {C:/Users/ZXR001/Desktop/vga_01/prj/db/pll_altpll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:51:12 on Mar 20,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/ZXR001/Desktop/vga_01/prj/db" C:/Users/ZXR001/Desktop/vga_01/prj/db/pll_altpll.v 
# -- Compiling module pll_altpll
# 
# Top level modules:
# 	pll_altpll
# End time: 18:51:12 on Mar 20,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+C:/Users/ZXR001/Desktop/vga_01/prj/../src {C:/Users/ZXR001/Desktop/vga_01/prj/../src/tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:51:12 on Mar 20,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/ZXR001/Desktop/vga_01/prj/../src" C:/Users/ZXR001/Desktop/vga_01/prj/../src/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 18:51:12 on Mar 20,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc"  tb
# End time: 18:51:13 on Mar 20,2021, Elapsed time: 0:14:47
# Errors: 0, Warnings: 0
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" tb 
# Start time: 18:51:13 on Mar 20,2021
# Loading work.tb
# Loading work.VGA_character
# Loading work.pll
# Loading altera_mf_ver.altpll
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading altera_mf_ver.pll_iobuf
# Loading altera_mf_ver.MF_cycloneiii_pll
# Loading altera_mf_ver.cda_m_cntr
# Loading altera_mf_ver.cda_n_cntr
# Loading altera_mf_ver.cda_scale_cntr
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.inst_VGA_01.pll_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 90000  Instance: tb.inst_VGA_01.pll_inst.altpll_component.cycloneiii_pll.pll3
# End time: 18:58:45 on Mar 20,2021, Elapsed time: 0:07:32
# Errors: 0, Warnings: 0
