# Reading D:/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl
# do VGA_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap work rtl_work 
# Copying D:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/ipcore {E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/ipcore/pll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 19:04:28 on Mar 23,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/ipcore" E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/ipcore/pll.v 
# -- Compiling module pll
# 
# Top level modules:
# 	pll
# End time: 19:04:28 on Mar 23,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/ipcore/rom {E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/ipcore/rom/rom.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 19:04:28 on Mar 23,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/ipcore/rom" E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/ipcore/rom/rom.v 
# -- Compiling module rom
# 
# Top level modules:
# 	rom
# End time: 19:04:28 on Mar 23,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/src {E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/src/VGA_bmp.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 19:04:28 on Mar 23,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/src" E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/src/VGA_bmp.v 
# -- Compiling module VGA_bmp
# 
# Top level modules:
# 	VGA_bmp
# End time: 19:04:28 on Mar 23,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/src {E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/src/read_rom.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 19:04:28 on Mar 23,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/src" E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/src/read_rom.v 
# -- Compiling module read_rom
# 
# Top level modules:
# 	read_rom
# End time: 19:04:28 on Mar 23,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/prj/db {E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/prj/db/pll_altpll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 19:04:29 on Mar 23,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/prj/db" E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/prj/db/pll_altpll.v 
# -- Compiling module pll_altpll
# 
# Top level modules:
# 	pll_altpll
# End time: 19:04:29 on Mar 23,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/prj/../src {E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/prj/../src/tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 19:04:29 on Mar 23,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/prj/../src" E:/course/1zhishiku_files/FPGA_VGA_5/vga_bmp/prj/../src/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 19:04:29 on Mar 23,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc"  tb
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" tb 
# Start time: 19:04:29 on Mar 23,2021
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./VGA_run_msim_rtl_verilog.do PAUSED at line 16
# End time: 19:04:52 on Mar 23,2021, Elapsed time: 0:00:23
# Errors: 0, Warnings: 0
