# Reading D:/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl
# do edge_detector_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap work rtl_work 
# Copying D:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+E:/course/1zhishiku_files/edge_detector/src {E:/course/1zhishiku_files/edge_detector/src/edge_detector_2.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 11:19:41 on Apr 16,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+E:/course/1zhishiku_files/edge_detector/src" E:/course/1zhishiku_files/edge_detector/src/edge_detector_2.v 
# -- Compiling module edge_detector_2
# 
# Top level modules:
# 	edge_detector_2
# End time: 11:19:42 on Apr 16,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+E:/course/1zhishiku_files/edge_detector/prj/../src {E:/course/1zhishiku_files/edge_detector/prj/../src/edge_detector_tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 11:19:42 on Apr 16,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+E:/course/1zhishiku_files/edge_detector/prj/../src" E:/course/1zhishiku_files/edge_detector/prj/../src/edge_detector_tb.v 
# -- Compiling module edge_detector_tb
# 
# Top level modules:
# 	edge_detector_tb
# End time: 11:19:42 on Apr 16,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc"  edge_detector_tb
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" edge_detector_tb 
# Start time: 11:19:43 on Apr 16,2021
# Loading work.edge_detector_tb
# Loading work.edge_detector_2
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
add wave -position insertpoint sim:/edge_detector_tb/inst_edge_detector_2/*
restart
run -all
vlog -vlog01compat -work work +incdir+E:/course/1zhishiku_files/edge_detector/src E:/course/1zhishiku_files/edge_detector/src/edge_detector_2.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 11:21:30 on Apr 16,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+E:/course/1zhishiku_files/edge_detector/src" E:/course/1zhishiku_files/edge_detector/src/edge_detector_2.v 
# -- Compiling module edge_detector_2
# 
# Top level modules:
# 	edge_detector_2
# End time: 11:21:30 on Apr 16,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.edge_detector_2
run -all
# End time: 21:12:53 on Apr 16,2021, Elapsed time: 9:53:10
# Errors: 0, Warnings: 0
