# Reading pref.tcl
# do test_uart_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap work rtl_work 
# Copying d:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/0510/uart_txrx/uart {D:/Academic/Yvonne/0510/uart_txrx/uart/tx.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:13:14 on May 18,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/0510/uart_txrx/uart" D:/Academic/Yvonne/0510/uart_txrx/uart/tx.v 
# -- Compiling module tx
# 
# Top level modules:
# 	tx
# End time: 18:13:14 on May 18,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/0510/uart_txrx/uart {D:/Academic/Yvonne/0510/uart_txrx/uart/baud_rate_en.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:13:14 on May 18,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/0510/uart_txrx/uart" D:/Academic/Yvonne/0510/uart_txrx/uart/baud_rate_en.v 
# -- Compiling module baud_rate_en
# 
# Top level modules:
# 	baud_rate_en
# End time: 18:13:14 on May 18,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/0510/uart_txrx/uart {D:/Academic/Yvonne/0510/uart_txrx/uart/uart.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:13:14 on May 18,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/0510/uart_txrx/uart" D:/Academic/Yvonne/0510/uart_txrx/uart/uart.v 
# -- Compiling module uart
# 
# Top level modules:
# 	uart
# End time: 18:13:14 on May 18,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/0510/uart_txrx/uart {D:/Academic/Yvonne/0510/uart_txrx/uart/uart_pll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:13:14 on May 18,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/0510/uart_txrx/uart" D:/Academic/Yvonne/0510/uart_txrx/uart/uart_pll.v 
# -- Compiling module uart_pll
# 
# Top level modules:
# 	uart_pll
# End time: 18:13:14 on May 18,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/0510/uart_txrx/uart {D:/Academic/Yvonne/0510/uart_txrx/uart/test_uart.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:13:14 on May 18,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/0510/uart_txrx/uart" D:/Academic/Yvonne/0510/uart_txrx/uart/test_uart.v 
# -- Compiling module test_uart
# 
# Top level modules:
# 	test_uart
# End time: 18:13:14 on May 18,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/0510/uart_txrx/uart {D:/Academic/Yvonne/0510/uart_txrx/uart/rx_more_one.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:13:14 on May 18,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/0510/uart_txrx/uart" D:/Academic/Yvonne/0510/uart_txrx/uart/rx_more_one.v 
# -- Compiling module rx_more_one
# 
# Top level modules:
# 	rx_more_one
# End time: 18:13:14 on May 18,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/0510/uart_txrx/uart/db {D:/Academic/Yvonne/0510/uart_txrx/uart/db/uart_pll_altpll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:13:14 on May 18,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/0510/uart_txrx/uart/db" D:/Academic/Yvonne/0510/uart_txrx/uart/db/uart_pll_altpll.v 
# -- Compiling module uart_pll_altpll
# 
# Top level modules:
# 	uart_pll_altpll
# End time: 18:13:14 on May 18,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/0510/uart_txrx/uart {D:/Academic/Yvonne/0510/uart_txrx/uart/tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:13:14 on May 18,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/0510/uart_txrx/uart" D:/Academic/Yvonne/0510/uart_txrx/uart/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 18:13:14 on May 18,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc"  tb
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" tb 
# Start time: 18:13:14 on May 18,2022
# Loading work.tb
# Loading work.test_uart
# Loading work.uart
# Loading work.uart_pll
# Loading altera_mf_ver.altpll
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading altera_mf_ver.pll_iobuf
# Loading work.baud_rate_en
# Loading work.tx
# Loading work.rx_more_one
# Loading altera_mf_ver.MF_cycloneiii_pll
# Loading altera_mf_ver.cda_m_cntr
# Loading altera_mf_ver.cda_n_cntr
# Loading altera_mf_ver.cda_scale_cntr
# ** Warning: (vsim-3015) [PCDPC] - Port size (1) does not match connection size (32) for port 'bt_en'. The port definition is at: D:/Academic/Yvonne/0510/uart_txrx/uart/baud_rate_en.v(9).
#    Time: 0 ps  Iteration: 0  Instance: /tb/test_uart_inst/uart_inst/bau_rate_en_inst File: D:/Academic/Yvonne/0510/uart_txrx/uart/uart.v Line: 43
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 80000  Instance: tb.test_uart_inst.uart_inst.uart_pll_inst.altpll_component.cycloneiii_pll.pll3
add wave -position insertpoint sim:/tb/test_uart_inst/*
add wave -position insertpoint sim:/tb/test_uart_inst/uart_inst/rx_more_one_inst/*
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# ** Warning: (vsim-3015) [PCDPC] - Port size (1) does not match connection size (32) for port 'bt_en'. The port definition is at: D:/Academic/Yvonne/0510/uart_txrx/uart/baud_rate_en.v(9).
#    Time: 0 ps  Iteration: 0  Instance: /tb/test_uart_inst/uart_inst/bau_rate_en_inst File: D:/Academic/Yvonne/0510/uart_txrx/uart/uart.v Line: 43
run -all
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 80000  Instance: tb.test_uart_inst.uart_inst.uart_pll_inst.altpll_component.cycloneiii_pll.pll3
# ** Note: $stop    : D:/Academic/Yvonne/0510/uart_txrx/uart/tb.v(25)
#    Time: 800 us  Iteration: 0  Instance: /tb
# Break in Module tb at D:/Academic/Yvonne/0510/uart_txrx/uart/tb.v line 25
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0510/uart_txrx/uart/tb.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:17:16 on May 18,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0510/uart_txrx/uart/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 18:17:16 on May 18,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0510/uart_txrx/uart/test_uart.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:17:20 on May 18,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0510/uart_txrx/uart/test_uart.v 
# -- Compiling module test_uart
# 
# Top level modules:
# 	test_uart
# End time: 18:17:20 on May 18,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# Loading work.tb
# Loading work.test_uart
# ** Warning: (vsim-3015) [PCDPC] - Port size (1) does not match connection size (32) for port 'bt_en'. The port definition is at: D:/Academic/Yvonne/0510/uart_txrx/uart/baud_rate_en.v(9).
#    Time: 0 ps  Iteration: 0  Instance: /tb/test_uart_inst/uart_inst/bau_rate_en_inst File: D:/Academic/Yvonne/0510/uart_txrx/uart/uart.v Line: 43
run -all
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 80000  Instance: tb.test_uart_inst.uart_inst.uart_pll_inst.altpll_component.cycloneiii_pll.pll3
# ** Note: $stop    : D:/Academic/Yvonne/0510/uart_txrx/uart/tb.v(25)
#    Time: 800 us  Iteration: 0  Instance: /tb
# Break in Module tb at D:/Academic/Yvonne/0510/uart_txrx/uart/tb.v line 25
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0510/uart_txrx/uart/tb.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:18:32 on May 18,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0510/uart_txrx/uart/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 18:18:32 on May 18,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0510/uart_txrx/uart/test_uart.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:18:32 on May 18,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0510/uart_txrx/uart/test_uart.v 
# -- Compiling module test_uart
# 
# Top level modules:
# 	test_uart
# End time: 18:18:33 on May 18,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# Loading work.tb
# Loading work.test_uart
# ** Warning: (vsim-3015) [PCDPC] - Port size (1) does not match connection size (32) for port 'bt_en'. The port definition is at: D:/Academic/Yvonne/0510/uart_txrx/uart/baud_rate_en.v(9).
#    Time: 0 ps  Iteration: 0  Instance: /tb/test_uart_inst/uart_inst/bau_rate_en_inst File: D:/Academic/Yvonne/0510/uart_txrx/uart/uart.v Line: 43
run -all
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 80000  Instance: tb.test_uart_inst.uart_inst.uart_pll_inst.altpll_component.cycloneiii_pll.pll3
# ** Note: $stop    : D:/Academic/Yvonne/0510/uart_txrx/uart/tb.v(25)
#    Time: 2 ms  Iteration: 0  Instance: /tb
# Break in Module tb at D:/Academic/Yvonne/0510/uart_txrx/uart/tb.v line 25
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0510/uart_txrx/uart/test_uart.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:24:52 on May 18,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0510/uart_txrx/uart/test_uart.v 
# -- Compiling module test_uart
# 
# Top level modules:
# 	test_uart
# End time: 18:24:52 on May 18,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# Loading work.test_uart
# ** Warning: (vsim-3015) [PCDPC] - Port size (1) does not match connection size (32) for port 'bt_en'. The port definition is at: D:/Academic/Yvonne/0510/uart_txrx/uart/baud_rate_en.v(9).
#    Time: 0 ps  Iteration: 0  Instance: /tb/test_uart_inst/uart_inst/bau_rate_en_inst File: D:/Academic/Yvonne/0510/uart_txrx/uart/uart.v Line: 43
run -all
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 80000  Instance: tb.test_uart_inst.uart_inst.uart_pll_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0510/uart_txrx/uart/test_uart.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 18:26:15 on May 18,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0510/uart_txrx/uart/test_uart.v 
# -- Compiling module test_uart
# 
# Top level modules:
# 	test_uart
# End time: 18:26:15 on May 18,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# Loading work.test_uart
# ** Warning: (vsim-3015) [PCDPC] - Port size (1) does not match connection size (32) for port 'bt_en'. The port definition is at: D:/Academic/Yvonne/0510/uart_txrx/uart/baud_rate_en.v(9).
#    Time: 0 ps  Iteration: 0  Instance: /tb/test_uart_inst/uart_inst/bau_rate_en_inst File: D:/Academic/Yvonne/0510/uart_txrx/uart/uart.v Line: 43
run -all
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 80000  Instance: tb.test_uart_inst.uart_inst.uart_pll_inst.altpll_component.cycloneiii_pll.pll3
# ** Note: $stop    : D:/Academic/Yvonne/0510/uart_txrx/uart/tb.v(25)
#    Time: 2 ms  Iteration: 0  Instance: /tb
# Break in Module tb at D:/Academic/Yvonne/0510/uart_txrx/uart/tb.v line 25
write format wave -window .main_pane.wave.interior.cs.body.pw.wf D:/Academic/Yvonne/0510/uart_txrx/uart/simulation/modelsim/wave.do
# End time: 11:10:40 on May 19,2022, Elapsed time: 16:57:26
# Errors: 0, Warnings: 1
