# Reading pref.tcl
# do rx_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap work rtl_work 
# Copying d:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/0428/uart {D:/Academic/Yvonne/0428/uart/rx.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 17:25:41 on May 03,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/0428/uart" D:/Academic/Yvonne/0428/uart/rx.v 
# -- Compiling module rx
# 
# Top level modules:
# 	rx
# End time: 17:25:41 on May 03,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/0428/uart {D:/Academic/Yvonne/0428/uart/tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 17:25:41 on May 03,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/0428/uart" D:/Academic/Yvonne/0428/uart/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 17:25:41 on May 03,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc"  tb
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" tb 
# Start time: 17:25:41 on May 03,2022
# Loading work.tb
# Loading work.rx
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 17:27:34 on May 03,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 17:27:34 on May 03,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tb
run -all
# GetModuleFileName: The specified module could not be found.
# 
# 
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 17:31:59 on May 03,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v 
# -- Compiling module tb
# ** Error: D:/Academic/Yvonne/0428/uart/tb.v(49): (vlog-2110) Illegal reference to net "tx".
# End time: 17:31:59 on May 03,2022, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 17:43:22 on May 03,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v 
# -- Compiling module tb
# ** Error: D:/Academic/Yvonne/0428/uart/tb.v(51): (vlog-2110) Illegal reference to net "tx".
# End time: 17:43:22 on May 03,2022, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 17:43:45 on May 03,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 17:43:45 on May 03,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 17:43:46 on May 03,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 17:43:46 on May 03,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 17:43:47 on May 03,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 17:43:47 on May 03,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 17:43:47 on May 03,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 17:43:47 on May 03,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tb
run -all
# GetModuleFileName: The specified module could not be found.
# 
# 
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 17:44:44 on May 03,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 17:44:44 on May 03,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tb
run -all
# GetModuleFileName: The specified module could not be found.
# 
# 
# ** Note: $stop    : D:/Academic/Yvonne/0428/uart/tb.v(44)
#    Time: 3050 ns  Iteration: 0  Instance: /tb
# Break in Module tb at D:/Academic/Yvonne/0428/uart/tb.v line 44
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 17:45:19 on May 03,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 17:45:19 on May 03,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tb
run -all
# GetModuleFileName: The specified module could not be found.
# 
# 
# ** Note: $stop    : D:/Academic/Yvonne/0428/uart/tb.v(44)
#    Time: 300050 ns  Iteration: 0  Instance: /tb
# Break in Module tb at D:/Academic/Yvonne/0428/uart/tb.v line 44
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 17:46:03 on May 03,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 17:46:03 on May 03,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tb
run -all
# GetModuleFileName: The specified module could not be found.
# 
# 
add wave -position insertpoint sim:/tb/rx_inst/*
restart
run -all
# GetModuleFileName: The specified module could not be found.
# 
# 
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/rx.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 17:53:47 on May 03,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/rx.v 
# -- Compiling module rx
# 
# Top level modules:
# 	rx
# End time: 17:53:47 on May 03,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.rx
run -all
# GetModuleFileName: The specified module could not be found.
# 
# 
vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:57:12 on May 04,2022
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/0428/uart/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 16:57:12 on May 04,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tb
run -all
# GetModuleFileName: The specified module could not be found.
# 
# 
write format wave -window .main_pane.wave.interior.cs.body.pw.wf D:/Academic/Yvonne/0428/uart/simulation/modelsim/wave.do
# End time: 17:08:56 on May 04,2022, Elapsed time: 23:43:15
# Errors: 0, Warnings: 0
