# Reading pref.tcl
# do com_mul_scrambler_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap work rtl_work 
# Copying d:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler {D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler/mul_scrambler.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 11:44:55 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler" D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler/mul_scrambler.v 
# -- Compiling module mul_scrambler
# 
# Top level modules:
# 	mul_scrambler
# End time: 11:44:55 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler {D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler/mul_descrambler.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 11:44:55 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler" D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler/mul_descrambler.v 
# -- Compiling module mul_descrambler
# 
# Top level modules:
# 	mul_descrambler
# End time: 11:44:55 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler {D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler/comp_mul_scrabler.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 11:44:55 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler" D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler/comp_mul_scrabler.v 
# -- Compiling module comp_mul_scrabler
# 
# Top level modules:
# 	comp_mul_scrabler
# End time: 11:44:55 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler {D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler/mul_scrambler_phy.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 11:44:55 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler" D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler/mul_scrambler_phy.v 
# -- Compiling module mul_scrambler_phy
# 
# Top level modules:
# 	mul_scrambler_phy
# End time: 11:44:55 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler {D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler/mul_descrambler_phy.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 11:44:55 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler" D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler/mul_descrambler_phy.v 
# -- Compiling module mul_descrambler_phy
# 
# Top level modules:
# 	mul_descrambler_phy
# End time: 11:44:55 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler {D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler/tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 11:44:55 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler" D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 11:44:55 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc"  tb
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" tb 
# Start time: 11:44:55 on Jan 02,2022
# Loading work.tb
# Loading work.comp_mul_scrabler
# Loading work.mul_scrambler
# Loading work.mul_scrambler_phy
# Loading work.mul_descrambler
# Loading work.mul_descrambler_phy
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'comp_mul_scrabler_inst'.  Expected 11, found 10.
#    Time: 0 ps  Iteration: 0  Instance: /tb/comp_mul_scrabler_inst File: D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler/tb.v Line: 247
# ** Warning: (vsim-3722) D:/Academic/Yvonne/1227/mul_additive_scrambler/additive_scrambler/tb.v(247): [TFMPC] - Missing connection for port 'rx_vld'.
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
# End time: 13:29:54 on Jan 02,2022, Elapsed time: 1:44:59
# Errors: 0, Warnings: 2
