# Reading pref.tcl
# do hs_txrx_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap work rtl_work 
# Copying d:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1231/high_speed_txrx {D:/Academic/Yvonne/1231/high_speed_txrx/trans_pma.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:02:22 on Dec 31,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1231/high_speed_txrx" D:/Academic/Yvonne/1231/high_speed_txrx/trans_pma.v 
# -- Compiling module trans_pma
# 
# Top level modules:
# 	trans_pma
# End time: 16:02:22 on Dec 31,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1231/high_speed_txrx {D:/Academic/Yvonne/1231/high_speed_txrx/rec_pcs.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:02:22 on Dec 31,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1231/high_speed_txrx" D:/Academic/Yvonne/1231/high_speed_txrx/rec_pcs.v 
# -- Compiling module rev_pcs
# 
# Top level modules:
# 	rev_pcs
# End time: 16:02:22 on Dec 31,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1231/high_speed_txrx {D:/Academic/Yvonne/1231/high_speed_txrx/recv_data.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:02:22 on Dec 31,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1231/high_speed_txrx" D:/Academic/Yvonne/1231/high_speed_txrx/recv_data.v 
# -- Compiling module recv_data
# 
# Top level modules:
# 	recv_data
# End time: 16:02:22 on Dec 31,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1231/high_speed_txrx {D:/Academic/Yvonne/1231/high_speed_txrx/recv_bit.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:02:22 on Dec 31,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1231/high_speed_txrx" D:/Academic/Yvonne/1231/high_speed_txrx/recv_bit.v 
# -- Compiling module recv_bit
# 
# Top level modules:
# 	recv_bit
# End time: 16:02:22 on Dec 31,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1231/high_speed_txrx {D:/Academic/Yvonne/1231/high_speed_txrx/trans_data.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:02:22 on Dec 31,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1231/high_speed_txrx" D:/Academic/Yvonne/1231/high_speed_txrx/trans_data.v 
# -- Compiling module trans_data
# 
# Top level modules:
# 	trans_data
# End time: 16:02:22 on Dec 31,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1231/high_speed_txrx {D:/Academic/Yvonne/1231/high_speed_txrx/IO_RX.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:02:22 on Dec 31,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1231/high_speed_txrx" D:/Academic/Yvonne/1231/high_speed_txrx/IO_RX.v 
# -- Compiling module IO_RX
# 
# Top level modules:
# 	IO_RX
# End time: 16:02:22 on Dec 31,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1231/high_speed_txrx {D:/Academic/Yvonne/1231/high_speed_txrx/IO_TX.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:02:22 on Dec 31,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1231/high_speed_txrx" D:/Academic/Yvonne/1231/high_speed_txrx/IO_TX.v 
# -- Compiling module IO_TX
# 
# Top level modules:
# 	IO_TX
# End time: 16:02:22 on Dec 31,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1231/high_speed_txrx {D:/Academic/Yvonne/1231/high_speed_txrx/hs_txrx.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:02:22 on Dec 31,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1231/high_speed_txrx" D:/Academic/Yvonne/1231/high_speed_txrx/hs_txrx.v 
# -- Compiling module hs_txrx
# 
# Top level modules:
# 	hs_txrx
# End time: 16:02:22 on Dec 31,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1231/high_speed_txrx {D:/Academic/Yvonne/1231/high_speed_txrx/pll1.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:02:23 on Dec 31,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1231/high_speed_txrx" D:/Academic/Yvonne/1231/high_speed_txrx/pll1.v 
# -- Compiling module pll1
# 
# Top level modules:
# 	pll1
# End time: 16:02:23 on Dec 31,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1231/high_speed_txrx/db {D:/Academic/Yvonne/1231/high_speed_txrx/db/pll1_altpll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:02:23 on Dec 31,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1231/high_speed_txrx/db" D:/Academic/Yvonne/1231/high_speed_txrx/db/pll1_altpll.v 
# -- Compiling module pll1_altpll
# 
# Top level modules:
# 	pll1_altpll
# End time: 16:02:23 on Dec 31,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1231/high_speed_txrx {D:/Academic/Yvonne/1231/high_speed_txrx/tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:02:23 on Dec 31,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1231/high_speed_txrx" D:/Academic/Yvonne/1231/high_speed_txrx/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 16:02:23 on Dec 31,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc"  tb
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" tb 
# Start time: 16:02:23 on Dec 31,2021
# Loading work.tb
# Loading work.hs_txrx
# Loading work.trans_data
# Loading work.trans_pma
# Loading work.IO_TX
# Loading altera_mf_ver.altlvds_tx
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading work.rev_pcs
# Loading work.recv_data
# Loading work.recv_bit
# Loading work.IO_RX
# Loading altera_mf_ver.altlvds_rx
# Loading altera_mf_ver.stratix_lvds_rx
# Loading altera_mf_ver.stratixgx_dpa_lvds_rx
# Loading altera_mf_ver.flexible_lvds_rx
# Loading work.pll1
# Loading altera_mf_ver.altpll
# Loading altera_mf_ver.pll_iobuf
# Loading altera_mf_ver.MF_cycloneiii_pll
# Loading altera_mf_ver.cda_m_cntr
# Loading altera_mf_ver.cda_n_cntr
# Loading altera_mf_ver.cda_scale_cntr
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
add wave -position insertpoint sim:/tb/hs_txrx_inst/trans_data_inst/*
restart
run
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
run
run -all
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
add wave -position insertpoint sim:/tb/hs_txrx_inst/trans_data_inst/trans_pma_inst/*
restart
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
add wave -position end  sim:/tb/hs_txrx_inst/recv_pcs_inst/sync
restart
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
# End time: 10:22:52 on Jan 02,2022, Elapsed time: 42:20:29
# Errors: 0, Warnings: 0
