# Reading pref.tcl
# do hs_txrx_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap work rtl_work 
# Copying d:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/IO_RX.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:19 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/IO_RX.v 
# -- Compiling module IO_RX
# 
# Top level modules:
# 	IO_RX
# End time: 12:50:19 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/IO_TX.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:20 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/IO_TX.v 
# -- Compiling module IO_TX
# 
# Top level modules:
# 	IO_TX
# End time: 12:50:20 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/hs_txrx.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:20 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/hs_txrx.v 
# -- Compiling module hs_txrx
# 
# Top level modules:
# 	hs_txrx
# End time: 12:50:20 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/pll1.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:20 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/pll1.v 
# -- Compiling module pll1
# 
# Top level modules:
# 	pll1
# End time: 12:50:20 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/encode_8b10b.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:20 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/encode_8b10b.v 
# -- Compiling module encode_8b10b
# 
# Top level modules:
# 	encode_8b10b
# End time: 12:50:20 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/trans_data_link.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:20 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/trans_data_link.v 
# -- Compiling module trans_data_link
# 
# Top level modules:
# 	trans_data_link
# End time: 12:50:20 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_data_phy.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:20 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_data_phy.v 
# -- Compiling module tx_data_phy
# 
# Top level modules:
# 	tx_data_phy
# End time: 12:50:20 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_pmd.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:20 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_pmd.v 
# -- Compiling module tx_PMD
# 
# Top level modules:
# 	tx_PMD
# End time: 12:50:20 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_PMA.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:20 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_PMA.v 
# -- Compiling module tx_PMA
# 
# Top level modules:
# 	tx_PMA
# End time: 12:50:20 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/recv_data_pma.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:20 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/recv_data_pma.v 
# -- Compiling module recv_data_pma
# 
# Top level modules:
# 	recv_data_pma
# End time: 12:50:20 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/recv_bit_pmd.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:20 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/recv_bit_pmd.v 
# -- Compiling module recv_bit_pmd
# 
# Top level modules:
# 	recv_bit_pmd
# End time: 12:50:20 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/decode_10b8b.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:20 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/decode_10b8b.v 
# -- Compiling module decode_10b8b
# 
# Top level modules:
# 	decode_10b8b
# End time: 12:50:20 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/rx_data_pcs.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:20 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/rx_data_pcs.v 
# -- Compiling module recv_data_pcs
# 
# Top level modules:
# 	recv_data_pcs
# End time: 12:50:20 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_pingpong_buffer.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:21 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_pingpong_buffer.v 
# -- Compiling module tx_pingpong_buffer
# 
# Top level modules:
# 	tx_pingpong_buffer
# End time: 12:50:21 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/recv_data_link.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:21 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/recv_data_link.v 
# -- Compiling module recv_data_link
# 
# Top level modules:
# 	recv_data_link
# End time: 12:50:21 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/db {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/db/pll1_altpll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:21 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/db" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/db/pll1_altpll.v 
# -- Compiling module pll1_altpll
# 
# Top level modules:
# 	pll1_altpll
# End time: 12:50:21 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tb_pinpong.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:50:21 on Dec 24,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tb_pinpong.v 
# -- Compiling module tb_pinpong
# 
# Top level modules:
# 	tb_pinpong
# End time: 12:50:21 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc"  tb_pinpong
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" tb_pinpong 
# Start time: 12:50:21 on Dec 24,2021
# Loading work.tb_pinpong
# Loading work.hs_txrx
# Loading work.trans_data_link
# Loading work.tx_pingpong_buffer
# Loading altera_mf_ver.altsyncram
# Loading work.tx_data_phy
# Loading work.encode_8b10b
# Loading work.tx_PMA
# Loading work.tx_PMD
# Loading work.IO_TX
# Loading altera_mf_ver.altlvds_tx
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading work.recv_data_link
# Loading work.recv_data_pcs
# Loading work.decode_10b8b
# Loading work.recv_data_pma
# Loading work.recv_bit_pmd
# Loading work.IO_RX
# Loading altera_mf_ver.altlvds_rx
# Loading altera_mf_ver.stratix_lvds_rx
# Loading altera_mf_ver.stratixgx_dpa_lvds_rx
# Loading altera_mf_ver.flexible_lvds_rx
# Loading work.pll1
# Loading altera_mf_ver.altpll
# Loading altera_mf_ver.pll_iobuf
# Loading altera_mf_ver.altsyncram_body
# Loading altera_mf_ver.ALTERA_MF_MEMORY_INITIALIZATION
# Loading altera_mf_ver.MF_cycloneiii_pll
# Loading altera_mf_ver.cda_m_cntr
# Loading altera_mf_ver.cda_n_cntr
# Loading altera_mf_ver.cda_scale_cntr
# 
# add wave *
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
#           File in use by: HW-PC  Hostname: DESKTOP-310O1JH  ProcessID: 292
#           Attempting to use alternate WLF file "./wlftym1y0i".
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
#           Using alternate file: ./wlftym1y0i
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.trans_data_link_inst.tx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.recv_data_link_inst.rx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tb_pinpong.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:58:54 on Dec 24,2021
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tb_pinpong.v 
# -- Compiling module tb_pinpong
# 
# Top level modules:
# 	tb_pinpong
# End time: 12:58:54 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# Loading work.tb_pinpong
run
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.trans_data_link_inst.tx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.recv_data_link_inst.rx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
run -all
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
add wave -position insertpoint sim:/tb_pinpong/hs_txrx_inst/recv_data_link_inst/*
restart
run -all
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.trans_data_link_inst.tx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.recv_data_link_inst.rx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
add wave -position insertpoint sim:/tb_pinpong/hs_txrx_inst/trans_data_link_inst/*
run
run -all
restart
run -all
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.trans_data_link_inst.tx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.recv_data_link_inst.rx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
add wave -position insertpoint sim:/tb_pinpong/hs_txrx_inst/recv_data_link_inst/recv_data_pcs_inst/*
restart
run -all
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.trans_data_link_inst.tx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.recv_data_link_inst.rx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_data_phy.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 13:57:55 on Dec 24,2021
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_data_phy.v 
# -- Compiling module tx_data_phy
# 
# Top level modules:
# 	tx_data_phy
# End time: 13:57:55 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tx_data_phy
run -all
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.trans_data_link_inst.tx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.recv_data_link_inst.rx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_data_phy.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 14:05:59 on Dec 24,2021
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_data_phy.v 
# -- Compiling module tx_data_phy
# 
# Top level modules:
# 	tx_data_phy
# End time: 14:05:59 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tx_data_phy
run -all
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.trans_data_link_inst.tx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.recv_data_link_inst.rx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tb_pinpong.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 14:08:11 on Dec 24,2021
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tb_pinpong.v 
# -- Compiling module tb_pinpong
# 
# Top level modules:
# 	tb_pinpong
# End time: 14:08:11 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tb_pinpong
run -all
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.trans_data_link_inst.tx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.recv_data_link_inst.rx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tb_pinpong.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:22:48 on Dec 24,2021
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tb_pinpong.v 
# -- Compiling module tb_pinpong
# 
# Top level modules:
# 	tb_pinpong
# End time: 15:22:48 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tb_pinpong
run -all
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.trans_data_link_inst.tx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.recv_data_link_inst.rx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tb_pinpong.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:26:15 on Dec 24,2021
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tb_pinpong.v 
# -- Compiling module tb_pinpong
# 
# Top level modules:
# 	tb_pinpong
# End time: 15:26:15 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tb_pinpong
run -all
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.trans_data_link_inst.tx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.recv_data_link_inst.rx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tb_pinpong.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:27:25 on Dec 24,2021
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tb_pinpong.v 
# -- Compiling module tb_pinpong
# 
# Top level modules:
# 	tb_pinpong
# End time: 15:27:25 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tb_pinpong
run -all
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.trans_data_link_inst.tx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.recv_data_link_inst.rx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tb_pinpong.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:46:11 on Dec 24,2021
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tb_pinpong.v 
# -- Compiling module tb_pinpong
# 
# Top level modules:
# 	tb_pinpong
# End time: 15:46:11 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tb_pinpong
run -all
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.trans_data_link_inst.tx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.recv_data_link_inst.rx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_data_phy.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:51:33 on Dec 24,2021
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_data_phy.v 
# -- Compiling module tx_data_phy
# 
# Top level modules:
# 	tx_data_phy
# End time: 15:51:33 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tx_data_phy
run -all
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.trans_data_link_inst.tx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.recv_data_link_inst.rx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
add wave -position insertpoint sim:/tb_pinpong/hs_txrx_inst/trans_data_link_inst/tx_data_phy_inst/*
restart
run -all
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.trans_data_link_inst.tx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.recv_data_link_inst.rx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_data_phy.v
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 16:49:40 on Dec 24,2021
# vlog -reportprogress 300 -work work D:/Academic/Yvonne/1221/high_speed_txrx_pcs8b10b/tx_data_phy.v 
# -- Compiling module tx_data_phy
# 
# Top level modules:
# 	tx_data_phy
# End time: 16:49:40 on Dec 24,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tx_data_phy
run -all
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.trans_data_link_inst.tx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.recv_data_link_inst.rx_pingpong_buffer_inst.altsyncram_component.m_default.altsyncram_inst
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb_pinpong.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
# End time: 15:20:06 on Dec 27,2021, Elapsed time: 74:29:45
# Errors: 0, Warnings: 0
