# Reading pref.tcl
# do hs_txrx_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap work rtl_work 
# Copying d:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/recv_data_link.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:51 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/recv_data_link.v 
# -- Compiling module recv_data_link
# 
# Top level modules:
# 	recv_data_link
# End time: 15:17:51 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/top.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:51 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/top.v 
# -- Compiling module top
# 
# Top level modules:
# 	top
# End time: 15:17:51 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/hs_txrx.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:51 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/hs_txrx.v 
# -- Compiling module hs_txrx
# 
# Top level modules:
# 	hs_txrx
# End time: 15:17:51 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/pll1.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:51 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/pll1.v 
# -- Compiling module pll1
# 
# Top level modules:
# 	pll1
# End time: 15:17:51 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/encode_8b10b.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:51 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/encode_8b10b.v 
# -- Compiling module encode_8b10b
# 
# Top level modules:
# 	encode_8b10b
# End time: 15:17:51 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/trans_data_link.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:51 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/trans_data_link.v 
# -- Compiling module trans_data_link
# 
# Top level modules:
# 	trans_data_link
# End time: 15:17:51 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/tx_data_phy.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:51 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/tx_data_phy.v 
# -- Compiling module tx_data_phy
# 
# Top level modules:
# 	tx_data_phy
# End time: 15:17:51 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/tx_pmd.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:51 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/tx_pmd.v 
# -- Compiling module tx_PMD
# 
# Top level modules:
# 	tx_PMD
# End time: 15:17:51 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/tx_PMA.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:51 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/tx_PMA.v 
# -- Compiling module tx_PMA
# 
# Top level modules:
# 	tx_PMA
# End time: 15:17:51 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/recv_data_pma.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:51 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/recv_data_pma.v 
# -- Compiling module recv_data_pma
# 
# Top level modules:
# 	recv_data_pma
# End time: 15:17:51 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/recv_bit_pmd.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:51 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/recv_bit_pmd.v 
# -- Compiling module recv_bit_pmd
# 
# Top level modules:
# 	recv_bit_pmd
# End time: 15:17:51 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/decode_10b8b.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:51 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/decode_10b8b.v 
# -- Compiling module decode_10b8b
# 
# Top level modules:
# 	decode_10b8b
# End time: 15:17:52 on Dec 10,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/rx_data_pcs.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:52 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/rx_data_pcs.v 
# -- Compiling module recv_data_pcs
# 
# Top level modules:
# 	recv_data_pcs
# End time: 15:17:52 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/IO_RX.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:52 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/IO_RX.v 
# -- Compiling module IO_RX
# 
# Top level modules:
# 	IO_RX
# End time: 15:17:52 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/IO_TX.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:52 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/IO_TX.v 
# -- Compiling module IO_TX
# 
# Top level modules:
# 	IO_TX
# End time: 15:17:52 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/db {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/db/pll1_altpll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:52 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/db" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/db/pll1_altpll.v 
# -- Compiling module pll1_altpll
# 
# Top level modules:
# 	pll1_altpll
# End time: 15:17:52 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b {D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/top.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 15:17:52 on Dec 10,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b" D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/top.v 
# -- Compiling module top
# 
# Top level modules:
# 	top
# End time: 15:17:52 on Dec 10,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc"  top
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" top 
# Start time: 15:17:52 on Dec 10,2021
# Loading work.top
# Loading work.hs_txrx
# Loading work.trans_data_link
# Loading work.tx_data_phy
# Loading work.encode_8b10b
# Loading work.tx_PMA
# Loading work.tx_PMD
# Loading work.IO_TX
# Loading altera_mf_ver.altlvds_tx
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading work.recv_data_link
# Loading work.recv_data_pcs
# Loading work.decode_10b8b
# Loading work.recv_data_pma
# Loading work.recv_bit_pmd
# Loading work.IO_RX
# Loading altera_mf_ver.altlvds_rx
# Loading altera_mf_ver.stratix_lvds_rx
# Loading altera_mf_ver.stratixgx_dpa_lvds_rx
# Loading altera_mf_ver.flexible_lvds_rx
# Loading work.pll1
# Loading altera_mf_ver.altpll
# Loading altera_mf_ver.pll_iobuf
# Loading altera_mf_ver.MF_cycloneiii_pll
# Loading altera_mf_ver.cda_m_cntr
# Loading altera_mf_ver.cda_n_cntr
# Loading altera_mf_ver.cda_scale_cntr
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'recv_bit_pmd_inst'.  Expected 8, found 5.
#    Time: 0 ps  Iteration: 0  Instance: /top/hs_txrx_inst/recv_data_link_inst/recv_data_pcs_inst/recv_data_pma_inst/recv_bit_pmd_inst File: D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/recv_data_pma.v Line: 167
# ** Warning: (vsim-3722) D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/recv_data_pma.v(167): [TFMPC] - Missing connection for port 'rx_r'.
# ** Warning: (vsim-3722) D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/recv_data_pma.v(167): [TFMPC] - Missing connection for port 'rx_rr'.
# ** Warning: (vsim-3722) D:/Academic/Yvonne/1210/high_speed_txrx_pcs8b10b/recv_data_pma.v(167): [TFMPC] - Missing connection for port 'rx_dg'.
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
# End time: 15:18:10 on Dec 10,2021, Elapsed time: 0:00:18
# Errors: 0, Warnings: 4
