module top_module(
    input clk,
    input areset,  
    input in,
    output out
);  

    parameter A=0, B=1; 
    reg state, next_state;


    always @(posedge clk, posedge areset) begin  
        if(areset)
            state <= B;
        else
        state <= next_state;
    end


    always @(*) begin   
        case(state)
        A:begin
            if(in == 1)
                next_state = A;
            else
                next_state = B;
           end
                    
        B:begin
             if(in == 1)
                 next_state = B;
            else
                next_state = A;
          end
        endcase
    end

    

    // Output logic
    assign out = (state ==B)? 1 : 0;

endmodule