module top_module(
    input clk,
    input areset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(posedge clk, posedge areset) begin
        if(areset)
            state <= OFF;
        else
            state <= next_state;
    end


    always @(*) begin
        case(state)
        OFF: 
        begin
            if(j == 1)
                next_state = ON;
            else
                next_state = OFF;
        end
        ON: 
        begin
            if( k == 1)
                next_state = OFF;
            else
                next_state = ON;
        end
        endcase
    end


    assign out = (state == OFF) ? 0 : 1;

endmodule