module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    reg st = 0;
    reg car = 1;
    
    always @ (posedge clk or posedge areset)
        if(areset)
        begin
            st <= 0;
    		car <= 1;
        end
        else
        begin
            case(st)
                0:
                    begin
                        st <= ~x + car; 
                        car <= ~x & car;
                    end
                1:
                    begin
                        st <= ~x + car; 
                        car <= ~x & car;
                    end
            endcase
        end
        
assign z = st;
        

endmodule