module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    reg[1:0] st;
    wire [1:0] nst;
    
    always @ (posedge clk or posedge areset)
        if(areset)
            st <= 1;
    else st <= nst;
    
    
    assign nst[0]= (st[0] & ~x);
    assign nst[1] = (st[0] & x) | st[1] ;
    
    
    assign z = (st[0] & x) | (st[1] & ~x);
    
  

endmodule