module top_module (
    input clk,
    input reset,      
    input data,
    output reg start_shifting
);

reg [1:0] st = 0;
    always @(posedge clk)
    if (reset)
    begin
        start_shifting <= 0;
        st <= 0;
    end
    else
    begin
        case(st)
        0:
        begin
            if(data) st <= 1;
        end
        1:
        begin
            if(data) st <= 2;
            else st <= 0;
        end
        2:
        begin
            if(~data) st <= 3;
            else st <= 2;
        end
        3:
        begin
            if(data) start_shifting <= 1;
            else st <= 0;
        end
        endcase
        
    end
        

endmodule