module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena
);
    reg [1:0] st;
    always @ (posedge clk)
        if(reset)
            begin
            st <= 0;
                shift_ena <= 1;
            end
    else
        begin
            case (st)
                0:
                    begin
                        st <= 1;
                    end
                1:
                    begin
                        st <= 2;
                    end
                2:
                    begin
                        st <= 3;
                        
                    end
                3:
                    begin
                        shift_ena <= 0;
                end
                
            endcase
        end
            

endmodule