module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack 
    );

    reg [3:0] st;


//detect sequence 1101
    always @ (posedge clk)
    if(reset)
    begin
        st <= 0;
        counting <= 0;
        done <= 0;
    end
    else
    begin
        case(st)
        0:
        begin
            if(data) st <= 1;
        end
        1:
        begin
            if(data) st <= 2;
            else st <= 0;
        end
        2:
        begin
            if(~data) st <= 3;
            else st <= 2;
        end
        3:
        begin
            if(data) 
            begin
                st <= 4;
                shift_ena <= 1;
            end
            else st <= 0;
        end

        4://shift 4 more bits, done_counting,and ack asserts
        begin
            st <= 5;
        end
        5:
        begin
            st <= 6;
        end
        6:
        begin
            st <= 7;
        end
        7:
        begin                   
            shift_ena <= 0;
            counting <= 1;
			st <= 8;

        end
        8:
        begin
            if(done_counting)
            begin
                counting <= 0;
                done <= 1;
                st <= 9;
            end
            
        end
        9:
        begin
            if(ack)
            begin
                done <= 0; 
                st <= 0;
            end
        end
        
    endcase
    end
        
    
   
endmodule