module top_module(
    input clk,
    input in,
    input reset,
    output out); 
	
    parameter A=0, B=1, C=2, D=3;
    
    reg [1:0] state;
    reg [1:0] next_state;
    
    always @(posedge clk)
        if(reset)
            state <= A;
    else
        state <= next_state;
    
    
    always @ (*)
    case(state)
    A:begin        
        if(in == 0)
            next_state = A;
        else
            next_state = B;
    end
        
    B:begin        
        if(in == 0)
            next_state = C;
        else
            next_state = B; 
    end
        
    C:begin        
        if(in == 0)
            next_state = A;
        else
            next_state = D;
    end
        
    D:begin        
        if(in == 0)
            next_state = C;
        else
            next_state = B;
    end
        endcase

    assign out = (state == D ) ? 1'b1 : 1'b0; 

endmodule