module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output reg shift_ena,
    output reg counting,
    input done_counting,
    output reg done,
    input ack );

reg [3:0] pattern = 0;    
reg [3:0] st = 0;
always @ (posedge clk)
if(reset)
begin
    pattern <= 0;
    shift_ena <= 0;
    counting <= 0;
    done <= 0;
    st <= 0;
end    
else case(st)
0:
begin
    done <= 0;
    shift_ena <= 0;
    pattern <= {pattern[2:0], data};
    
    if({pattern[2:0], data} == 4'b1101)
    begin
        shift_ena <= 1;
        st <= 1;
    end
end
1:
begin
    shift_ena <= 1;
    st <= 2;
end
2:
begin
    shift_ena <= 1;
    st <= 3;
end
3:
begin
    shift_ena <= 1;
    st <= 4;
end
4:
begin
    shift_ena <= 0;
    counting <= 1;
    st <= 5;
end
5:
begin
    if(done_counting)
    begin
        counting <= 0;
        done <= 1;
        st <= 6;
    end
end
6:
begin
    if(ack)
    begin
        done <= 0;
        pattern <= 0;
        st <= 0;
    end
end
default : st <= 0;
endcase
endmodule