module top_module (
    input clk,
    input reset,      
    input data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input ack 
    );

reg start = 0;
reg [9:0] dly_cnt = 999;
always @ (posedge clk)
if(!start) dly_cnt <= 999;
else
begin
    if(|dly_cnt) dly_cnt <= dly_cnt - 1;
    else dly_cnt <= 999;
end

wire dly_1000 = (dly_cnt == 0) ? 1'b1 : 1'b0;
    
reg [3:0] pattern = 0;    
reg [3:0] st = 0;
always @ (posedge clk)
if(reset)
begin
    counting <= 0;
    done <= 0;
    pattern <= 0;
    start <= 0;
    st <= 0;
end
else case (st)
0:
begin
    counting <= 0;
    done <= 0;
    start <= 0;

    pattern <= {pattern[2:0], data};
    if({pattern[2:0], data} == 4'b1101)
    begin
        pattern <= 0;
        st <= 1;
    end
end
1:
begin
    count <= {count[2:0], data};
    st <= 2;
end
2:
begin
    count <= {count[2:0], data};
    st <= 3;
end
3:
begin
    count <= {count[2:0], data};
    st <= 4;
end
4:
begin
    count <= {count[2:0], data};
    counting <= 1;
    start <= 1;
    st <= 6;
end
6:
begin
    if(dly_1000)
    begin
        if(|count) 
        begin
            count <= count - 1;
        end
        else 
        begin
            counting <= 0;
            done <= 1;
            st <= 7;    
        end
    end
end
7:
begin
    start <= 0;
    if(ack)
    begin
        done <= 0;
        st <= 0;
    end
end
default : st <= 0;
endcase
    
endmodule