module top_module(
    input clk,
    input [7:0] in,
    input reset,  
    output done
); 

    reg [1:0] state,next_state;
   

    always @ (*)
    begin
        case(state)
        0:
        begin
            if(in[3])
                next_state = 1;
            else
                next_state = 0;
        end
        1:
        begin
            next_state = 2;    
        end
        2:
        begin
            next_state = 3;
        end
        3:
        begin
            if(in[3])
                next_state = 1;
            else
                next_state = 0;
        end
        endcase
    end
    

    always @ (posedge clk)
        if(reset)
            state <= 0;
        else
            state <= next_state;
 
    assign done = (state == 3);

endmodule