module top_module(
    input clk,
    input [7:0] in,
    input reset,    
    output reg [23:0] out_bytes,
    output done
);
    
 reg [1:0] state,next_state;
    reg [23:0] bytes_temp;
   

    always @ (*)
    begin
        case(state)
        0:
        begin
            if(in[3])
            begin
                next_state = 1;
                bytes_temp[23:16]= in;
            end
            else
                next_state = 0;
        end
        1:
        begin
            next_state = 2;    
            bytes_temp[15:8] = in;
        end
        2:
        begin
            next_state = 3;
            bytes_temp[7:0] = in;
        end
        3:
        begin
            if(in[3])
            begin
                next_state = 1;
                bytes_temp[23:16] = in;
            end
            else
                next_state = 0;   
        end
        endcase
    end
    

    always @ (posedge clk)
        if(reset)
            state <= 0;
        else
            state <= next_state;
    
    always @ (posedge clk)
        if (done | reset)
            out_bytes <= 32'b0;
        else if(state == 2 )
			out_bytes <= bytes_temp;
            
 
    assign done = (state == 3);

endmodule