module top_module (
    input clk,
    input d,
    output q
);

reg clk_p = 0;    
    always @ (posedge clk)
        clk_p <= ~clk_p;
    
reg clk_n = 0;    
    always @ (negedge clk)
        clk_n <= ~clk_n;
    
wire clk_w = clk_p ^ clk_n;    
    
reg pos = 0;    
    always @ (posedge clk)
        pos <= d;
reg neg = 0;    
    always @ (negedge clk)
        neg <= d;
    
assign q = clk_w ? pos : neg;

endmodule