module top_module (
    input clk,
    input resetn,  
    input in,
    output out
);
    
    reg[3:0] shift;
    
    always @(posedge clk)
    if (~resetn)
	shift <= 0;
    else
        shift<= {in,shift[3:1]};
    
    assign out = shift[0];
    

endmodule