module top_module (
    input clk,
    input aresetn,    
    input x,
    output z ); 
    
    reg [1:0] st;
    
    always @(posedge clk or negedge aresetn)
    if(~aresetn)
       st <= 0;
    else
    begin
        case(st)
        0:
        begin
            if(x)
                st <= 1;
        end
        1:
        begin
            if(~x)
                st <= 2;
            else
                st <= 0;
        end
        2:
        begin
            if(x)
                st <= 1;
            else
                st <= 0;
            
        end
        
        endcase
    end

        assign z = (st == 2) && ( x );
    

endmodule