# Reading D:/intelFPGA_lite/18.0/modelsim_ase/tcl/vsim/pref.tcl
# do hs_txrx_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap work rtl_work 
# Copying D:/intelFPGA_lite/18.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj {D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:01:01 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj" D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v 
# -- Compiling module tx_pcs
# 
# Top level modules:
# 	tx_pcs
# End time: 16:01:01 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj {D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:01:01 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj" D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v 
# -- Compiling module trans_pma
# 
# Top level modules:
# 	trans_pma
# End time: 16:01:01 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj {D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/rec_pcs.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:01:01 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj" D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/rec_pcs.v 
# -- Compiling module rev_pcs
# 
# Top level modules:
# 	rev_pcs
# End time: 16:01:01 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj {D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:01:01 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj" D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v 
# -- Compiling module recv_data
# 
# Top level modules:
# 	recv_data
# End time: 16:01:01 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj {D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_bit.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:01:01 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj" D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_bit.v 
# -- Compiling module recv_bit
# 
# Top level modules:
# 	recv_bit
# End time: 16:01:01 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj {D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/IO_RX.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:01:01 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj" D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/IO_RX.v 
# -- Compiling module IO_RX
# 
# Top level modules:
# 	IO_RX
# End time: 16:01:01 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj {D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/IO_TX.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:01:01 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj" D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/IO_TX.v 
# -- Compiling module IO_TX
# 
# Top level modules:
# 	IO_TX
# End time: 16:01:01 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj {D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/hs_txrx.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:01:01 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj" D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/hs_txrx.v 
# -- Compiling module hs_txrx
# 
# Top level modules:
# 	hs_txrx
# End time: 16:01:01 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj {D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/pll1.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:01:01 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj" D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/pll1.v 
# -- Compiling module pll1
# 
# Top level modules:
# 	pll1
# End time: 16:01:01 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/db {D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/db/pll1_altpll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:01:01 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/db" D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/db/pll1_altpll.v 
# -- Compiling module pll1_altpll
# 
# Top level modules:
# 	pll1_altpll
# End time: 16:01:01 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj {D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:01:01 on Jan 02,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj" D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 16:01:01 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc"  tb
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" tb 
# Start time: 16:01:01 on Jan 02,2022
# Loading work.tb
# Loading work.hs_txrx
# Loading work.tx_pcs
# Loading work.trans_pma
# Loading work.IO_TX
# Loading altera_mf_ver.altlvds_tx
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading work.rev_pcs
# Loading work.recv_data
# Loading work.recv_bit
# Loading work.IO_RX
# Loading altera_mf_ver.altlvds_rx
# Loading altera_mf_ver.stratix_lvds_rx
# Loading altera_mf_ver.stratixgx_dpa_lvds_rx
# Loading altera_mf_ver.flexible_lvds_rx
# Loading work.pll1
# Loading altera_mf_ver.altpll
# Loading altera_mf_ver.pll_iobuf
# Loading altera_mf_ver.MF_cycloneiii_pll
# Loading altera_mf_ver.cda_m_cntr
# Loading altera_mf_ver.cda_n_cntr
# Loading altera_mf_ver.cda_scale_cntr
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
add wave -position insertpoint sim:/tb/hs_txrx_inst/recv_pcs_inst/*
add wave -position insertpoint sim:/tb/hs_txrx_inst/recv_pcs_inst/recv_data_inst/*
restart
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:05:20 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v 
# -- Compiling module recv_data
# 
# Top level modules:
# 	recv_data
# End time: 16:05:21 on Jan 02,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
restart
# Loading work.recv_data
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:08:28 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v 
# -- Compiling module tx_pcs
# 
# Top level modules:
# 	tx_pcs
# End time: 16:08:28 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tx_pcs
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/rec_pcs.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:10:32 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/rec_pcs.v 
# -- Compiling module rev_pcs
# 
# Top level modules:
# 	rev_pcs
# End time: 16:10:32 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.rev_pcs
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
write format wave -window .main_pane.wave.interior.cs.body.pw.wf D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/simulation/modelsim/wave.do
add wave -position insertpoint sim:/tb/hs_txrx_inst/tx_pcs_inst/*
restart
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:22:22 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v 
# -- Compiling module recv_data
# ** Error: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v(67): (vlog-2730) Undefined variable: 'fr_sync'.
# ** Error (suppressible): D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v(185): (vlog-2388) 'fr_sync' already declared in this scope (recv_data).
# End time: 16:22:22 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 2, Warnings: 0
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:23:00 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v 
# -- Compiling module recv_data
# 
# Top level modules:
# 	recv_data
# End time: 16:23:00 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.recv_data
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:23:37 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v 
# -- Compiling module recv_data
# 
# Top level modules:
# 	recv_data
# End time: 16:23:37 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.recv_data
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:59:50 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v 
# -- Compiling module tx_pcs
# 
# Top level modules:
# 	tx_pcs
# End time: 16:59:50 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tx_pcs
# Warning in wave window restart: (vish-4014) No objects found matching '/tb/hs_txrx_inst/tx_pcs_inst/tx_data_temp'. 
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
restart
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 17:06:20 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v 
# -- Compiling module tx_pcs
# 
# Top level modules:
# 	tx_pcs
# End time: 17:06:20 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tx_pcs
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 17:08:09 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v 
# -- Compiling module tx_pcs
# 
# Top level modules:
# 	tx_pcs
# End time: 17:08:09 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tx_pcs
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 17:15:42 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v 
# -- Compiling module tx_pcs
# 
# Top level modules:
# 	tx_pcs
# End time: 17:15:42 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tx_pcs
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
write format wave -window .main_pane.wave.interior.cs.body.pw.wf D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/simulation/modelsim/wave.do
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/hs_txrx.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:24:23 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/hs_txrx.v 
# -- Compiling module hs_txrx
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/hs_txrx.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	hs_txrx
# End time: 18:24:23 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:24:29 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v 
# -- Compiling module trans_pma
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	trans_pma
# End time: 18:24:29 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:24:31 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v 
# -- Compiling module tx_pcs
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	tx_pcs
# End time: 18:24:31 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/rec_pcs.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:24:36 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/rec_pcs.v 
# -- Compiling module rev_pcs
# 
# Top level modules:
# 	rev_pcs
# End time: 18:24:36 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_bit.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:24:38 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_bit.v 
# -- Compiling module recv_bit
# 
# Top level modules:
# 	recv_bit
# End time: 18:24:38 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:24:40 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v 
# -- Compiling module recv_data
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	recv_data
# End time: 18:24:40 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
restart
# Loading work.hs_txrx
# Loading work.tx_pcs
# Loading work.trans_pma
# Loading work.rev_pcs
# Loading work.recv_data
# Loading work.recv_bit
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/rec_pcs.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:26:28 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/rec_pcs.v 
# -- Compiling module rev_pcs
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/rec_pcs.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	rev_pcs
# End time: 18:26:28 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:26:30 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v 
# -- Compiling module recv_data
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	recv_data
# End time: 18:26:30 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
restart
# Loading work.rev_pcs
# Loading work.recv_data
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
add wave -position insertpoint sim:/tb/hs_txrx_inst/tx_pcs_inst/trans_pma_inst/*
write format wave -window .main_pane.wave.interior.cs.body.pw.wf D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/simulation/modelsim/wave.do
restart
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:31:44 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v 
# -- Compiling module trans_pma
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	trans_pma
# End time: 18:31:44 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:31:46 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v 
# -- Compiling module recv_data
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	recv_data
# End time: 18:31:46 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
restart
# Loading work.trans_pma
# Loading work.recv_data
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:33:22 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v 
# -- Compiling module recv_data
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	recv_data
# End time: 18:33:23 on Jan 02,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 1
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:33:25 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v 
# -- Compiling module trans_pma
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	trans_pma
# End time: 18:33:25 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
restart
# Loading work.trans_pma
# Loading work.recv_data
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:36:34 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v 
# -- Compiling module recv_data
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	recv_data
# End time: 18:36:34 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/rec_pcs.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:36:37 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/rec_pcs.v 
# -- Compiling module rev_pcs
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/rec_pcs.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	rev_pcs
# End time: 18:36:37 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:36:42 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v 
# -- Compiling module tx_pcs
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	tx_pcs
# End time: 18:36:42 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tb.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:36:46 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 18:36:46 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/hs_txrx.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:36:51 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/hs_txrx.v 
# -- Compiling module hs_txrx
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/hs_txrx.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	hs_txrx
# End time: 18:36:51 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:36:59 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v 
# -- Compiling module trans_pma
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	trans_pma
# End time: 18:36:59 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
restart
# Loading work.tb
# Loading work.hs_txrx
# Loading work.tx_pcs
# Loading work.trans_pma
# Loading work.rev_pcs
# Loading work.recv_data
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/hs_txrx.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:39:16 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/hs_txrx.v 
# -- Compiling module hs_txrx
# 
# Top level modules:
# 	hs_txrx
# End time: 18:39:16 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:39:21 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v 
# -- Compiling module recv_data
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_data.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	recv_data
# End time: 18:39:21 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:39:22 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v 
# -- Compiling module trans_pma
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/trans_pma.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	trans_pma
# End time: 18:39:22 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:39:24 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v 
# -- Compiling module tx_pcs
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/tx_pcs.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	tx_pcs
# End time: 18:39:25 on Jan 02,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 1
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_bit.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:39:28 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/recv_bit.v 
# -- Compiling module recv_bit
# 
# Top level modules:
# 	recv_bit
# End time: 18:39:28 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/rec_pcs.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:39:30 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/rec_pcs.v 
# -- Compiling module rev_pcs
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/rec_pcs.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	rev_pcs
# End time: 18:39:30 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
restart
# Loading work.hs_txrx
# Loading work.tx_pcs
# Loading work.trans_pma
# Loading work.rev_pcs
# Loading work.recv_data
# Loading work.recv_bit
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/hs_txrx.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 18:41:45 on Jan 02,2022
# vlog -reportprogress 300 -work work D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/hs_txrx.v 
# -- Compiling module hs_txrx
# ** Warning: D:/class/scramble/mul_additive_scrambler/multi_scrambler_prj/hs_txrx.v(3): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	hs_txrx
# End time: 18:41:45 on Jan 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
restart
# Loading work.hs_txrx
run -all
#  Note : Cyclone 10 LP PLL was reset
# Time: 0  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 140000  Instance: tb.hs_txrx_inst.pll1_inst.altpll_component.cycloneiii_pll.pll3
# End time: 10:06:39 on Jan 03,2022, Elapsed time: 18:05:38
# Errors: 2, Warnings: 20
