module top_module (
    input [2:0] r,
    input L,
    input clk, 

    output [2:0] Q
); 

    always @ (posedge clk)
    begin
        if(L)
            Q <= {r[2:0]};
        else
           Q <= {Q[1]^Q[2],Q[0],Q[2]};
    end

endmodule