module top_module (
    input clk,
    input [7:0] in,
    output reg [7:0] pedge
);
    reg [7:0] in_r;
    always @ (posedge clk)
        in_r <= in;
    
    always @ (posedge clk)
        begin
        pedge <= 0;
            
            if ({in[0],in_r[0]} == 2'b10) pedge[0] <= 1;
            if ({in[1],in_r[1]} == 2'b10) pedge[1] <= 1;
            if ({in[2],in_r[2]} == 2'b10) pedge[2] <= 1;
            if ({in[3],in_r[3]} == 2'b10) pedge[3] <= 1;
            if ({in[4],in_r[4]} == 2'b10) pedge[4] <= 1;
            if ({in[5],in_r[5]} == 2'b10) pedge[5] <= 1;
            if ({in[6],in_r[6]} == 2'b10) pedge[6] <= 1;
            if ({in[7],in_r[7]} == 2'b10) pedge[7] <= 1;
        end
        

endmodule