module top_module(
    input clk,
    input reset,    
    input in,
    output reg disc,
    output reg flag,
    output reg err
);
    reg [9:0] state = 0;
    reg [9:0] next_state = 0;
    
    always @ (posedge clk)
        if (reset)
            state <= 0;
        else
            state <= next_state;
    
    always @ (*)
    begin
        disc = 0;
        flag = 0;
        err = 0;
        
        case(state)
        0:
        begin
            if(in) next_state = 1;
            else next_state = 0;
        end
        1:
        begin
            if(in) next_state = 2;
            else next_state = 0;
        end
        2:
        begin
            if(in) next_state = 3;
            else next_state = 0;
        end
        3:
        begin
            if(in) next_state = 4;
            else next_state = 0;
        end
        4:
        begin
            if(in) next_state = 5;
            else next_state = 0;
        end
        5:
        begin
            if(in) next_state = 6;
            else next_state = 8;
        end
        6:
        begin
            if(in) next_state = 7;
            else next_state = 9;
        end
        7:
        begin
            err = 1;
            if(in) next_state = 7;
            else next_state = 0;
        end
        8:
        begin
            disc = 1;
            if(in) next_state = 1;
            else next_state = 0;
        end
        9:
        begin
            flag = 1;
            if(in) next_state = 1;
            else next_state = 0;
        end
        
        endcase
    end
    

endmodule