module top_module(
    input clk,
    input reset,   //同步高电平复位
    input in,
    output disc,
    output flag,
    output err);

    reg [7:0] data;    
always @ (posedge clk)
if(reset)    
    data  <= 0;
else
    data <= {data[6:0], in};


    assign err = (data[6:0] == 7'b111111_1);
    assign disc = (data[6:0] == 7'b011111_0) ;
    assign flag = (data == 8'b0111111_0) ;

endmodule