module top_module(
    input clk,
    input [7:0] in,
    input reset,  
    output done
); 
    reg [2:0] kkk;
    always @ (posedge clk )
        if(reset) kkk <= 0;
    else
    begin
        if(in[3] && ((kkk == 0) || done ))  kkk <= 3'b001;
        else  kkk <= {kkk[1:0], 1'b0};
    end
        
    
    assign done = kkk[2];        
        
endmodule