module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //

    reg [23:0] data;
    reg [2:0] kkk;
    always @ (posedge clk )
        if(reset) kkk <= 0;
    else
    begin
        if(in[3] && ((kkk == 0) || done )) 
        begin
            kkk <= 3'b001;
            data <= {16'h00, in};
        end
        else
        begin
            kkk <= {kkk[1:0], 1'b0};
            data <= {data[15:0], in};
        end
    end
        
    
    assign done = kkk[2];        
    assign  out_bytes = data;
        
endmodule