module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    
reg [31:0] in_r;
    
always @(posedge clk)
    in_r <= in;
    
    integer i ;
always @(posedge clk)
if(reset)
begin
    out <= 0;
end
else
begin
    for(i = 0 ; i < 32 ; i = i + 1)
        if({in_r[i],in[i]} == 2'b10)
            out[i] <= 1;
end

endmodule