module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);
    reg[3:0] shift = 0;
    
    always @(posedge clk )
    if(reset) 	shift<= 4'b1111;
    else        shift<={shift[2:0],1'b0};
    
    assign shift_ena = shift[3];
endmodule