`timescale 1ns / 1ps

module tb(

    );
reg clk = 1;

always #5 clk = ~clk;

reg reset = 0;
reg in = 0;
wire out;
wire st_out;

initial
begin
in  <= 1;
#300;
reset <= 1;
#10 reset <= 0;

#10 in <= 0;
#10 in <= 0;
#10 in <= 1;
#10 in <= 1;
#10 in <= 0;
#10 in <= 0;
#10 in <= 1;
#10 in <= 1;
#10 in <= 0;
#10 in <= 1;

#40;
#10 in <= 0;
#10 in <= 0;
#10 in <= 1;
#10 in <= 1;
#10 in <= 0;
#10 in <= 0;
#10 in <= 1;
#10 in <= 1;
#10 in <= 0;
#10 in <= 0;
#10 in <= 0;
#10 in <= 1;
#10 in <= 1;

#10 in <= 0;
#10 in <= 0;
#10 in <= 1;
#10 in <= 1;
#10 in <= 0;
#10 in <= 0;
#10 in <= 1;
#10 in <= 1;
#10 in <= 1;
#10 in <= 1;




#300;
$stop;
end    
    
    
// testbench top_inst(
// .clk(clk),
// .reset(reset),  
// .in(in),
// .out(out)
// ); 


st_testbench st_testbench_inst(
.clk(clk), 
.reset(reset), 
.in(in),
.done(st_out)
);
endmodule