`timescale 1ns / 1ps

module tb(

    );
reg clk = 0;

always #5 clk = ~clk;

reg areset = 0;
reg in = 0;
wire out;
wire st_out;

initial
begin
in  = 1;
#300;
areset = 1;
#12 areset = 0;

#10 in = 0;
#10 in = 0;
#10 in = 1;
#10 in = 1;
#10 in = 0;
#10 in = 0;
#10 in = 1;


#300;
$stop;
end    
    
    
testbench top_inst(
.clk(clk),
.areset(areset),  
.in(in),
.out(out)
); 


st_testbench st_testbench_inst(
.clk(clk), 
.areset(areset), 
.in(in),
.out(st_out)
);
endmodule