`timescale 1ns / 1ps

module tb(

    );
reg clk = 0;
reg  in = 0;

wire [3:0] q1,q2;
always #5 clk = ~clk;

reg shift_ena = 0;
reg count_ena = 0;

initial
begin

shift_ena <= 0;
count_ena <= 0;
#40;
@(posedge clk); 
in <= 1;
shift_ena <= 1;
@(posedge clk); 
in <= 0;
@(posedge clk); 
in <= 0;
@(posedge clk); 
in <= 1;
@(posedge clk); 
shift_ena <= 0;
in <= 0;

#40;
@(posedge clk); 
count_ena <= 1;
@(posedge clk); 
@(posedge clk); 
@(posedge clk); 
@(posedge clk); 
@(posedge clk); 
count_ena <= 0;



#100;
$stop;


end
    


testbench testbench_inst(
.clk(clk),
.shift_ena(shift_ena),
.count_ena(count_ena),
.data(in),
. q(q2)
); 
endmodule