`timescale 1ns / 1ps


module tb2(

    );
reg clk = 0;

always #5 clk = ~clk;

reg areset = 0;
reg j = 0;
reg k = 0;
wire out;

initial
begin
#303;
areset = 1;
#12 areset = 0;

@(posedge clk) j = 1;
#30 j = 0;
#10 k = 1;
#20 j = 1;
end    
    
    
top_module top_inst(
.clk(clk),
.areset(areset),  
.j(j),
.k(k),
.out(out)
); 
endmodule