`timescale 1ns / 1ps

module tb(

    );
reg clk = 0;
reg  in = 0;
reg reset = 0;

wire start_shifting1,start_shifting2;
always #5 clk = ~clk;


initial
begin

reset = 1;
#40;
@(posedge clk); 
reset = 0;
@(posedge clk); 
in <= 1;
@(posedge clk); 
in <= 0;
@(posedge clk); 
in <= 1;
@(posedge clk); 
in <= 1;
@(posedge clk); 
in <= 1;
@(posedge clk); 
in <= 1;
@(posedge clk); 
in <= 1;
@(posedge clk); 
in <= 0;
@(posedge clk); 
in <= 1;
@(posedge clk); 
in <= 1;
@(posedge clk); 
in <= 0;
@(posedge clk); 
in <= 0;
@(posedge clk); 
in <= 1;
reset <= 1;


#100;
$stop;


end
    

testbench testbench_inst(
.clk(clk),
.reset(reset),
.data(in),
.start_shifting(start_shifting2)
); 
endmodule