`timescale 1ns / 1ps

module tb(

    );
    
    

    
reg clk = 0;
always #5 clk = ~clk;

reg do_sub = 0;
reg [7:0] a = 0;
reg [7:0] b = 0;

wire [7:0] out;
wire [7:0] st_out;
wire result_is_zero;
wire st_result_is_zero;


initial
begin

    do_sub <= 0;
    a <= 8'haa;
    b <= 8'hbb;
    @(posedge clk);
    @(posedge clk);
    do_sub <= 1;
    @(posedge clk);
    @(posedge clk);
    do_sub <= 0;
    a <= 8'h03;
    b <= 8'h03;
    @(posedge clk);
    @(posedge clk);
    do_sub <= 1;
    @(posedge clk);
    do_sub <= 0;
    b <= 8'h04;
    @(posedge clk);
    @(posedge clk);
    do_sub <= 1;
    @(posedge clk);
    do_sub <= 0;
    a <= 8'hfd;
    b <= 8'h03;

    @(posedge clk);
    @(posedge clk);
    do_sub <= 1;
    @(posedge clk);
    do_sub <= 0;
    b <= 8'h04;

    
    #200;
    $stop;

end
    
testbench  testbench_inst 
(
    .do_sub     (do_sub),
    .a          (a),      // Synchronous reset
    .b          (b),
    
    .out        (out),
    .result_is_zero    (result_is_zero)
);




//top_module  top_module_inst 
//(
//    .clk    (clk),
//    .reset  (reset),      // Synchronous reset
//    .data   (data),
//    
//    .shift_ena  (st_shift_ena),
//    .counting   (st_counting),
//    
//    .done_counting  (done_counting),
//    .done   (st_done),
//    .ack    (ack)
//);

    
endmodule