`timescale 1ns / 1ps

module tb(

    );
reg clk = 1;

always #5 clk = ~clk;

reg areset = 0;
reg in = 0;
wire z;

initial
begin
in  <= 0;
areset <= 0;
#300;

areset <= 1;
#7 areset <= 0;
@(posedge clk);
#10 in <= 0;
#10 in <= 0;
#10 in <= 0;
#10 in <= 1;
#10 in <= 0;
#10 in <= 1;
#10 in <= 1;
#10 in <= 0;
#10 in <= 0;

#41;
areset <= 1;
#7 areset <= 0;
@(posedge clk);
#10 in <= 0;
#10 in <= 0;
#10 in <= 1;
#10 in <= 1;
#10 in <= 1;
#10 in <= 0;
#10 in <= 1;
#10 in <= 0;

#300;
$stop;
end    
    
    
// testbench top_inst(
// .clk(clk),
// .areset(areset),  
// .in(in),
// .out(out)
// ); 


st_testbench st_testbench_inst(
.clk(clk), 
.areset(areset), 
.x(in),
.z(z)
);
endmodule