`timescale 1ns / 1ps

module tb6(

    );
reg in = 0;
reg [3:0] st = 0;
wire [3:0] nst;
wire out;

initial
begin
in = 1;
st = 1;
#10;
st = 2;
#20;
in = 0;
#10;
in = 1;
#10;
st = 4;
#10;
in = 0;
st = 2;
#30;
in = 1;
#10;
st = 4;

end
    
    
top_module top_inst(
.in(in),
.state(st),
.next_state(nst),
.out(out)
); 
endmodule