`timescale 1ns / 1ps

module tb(

    );
    
    

    
reg clk = 0;
reg  in = 0;

always #5 clk = ~clk;

reg reset = 1;
reg data = 0;
wire [3:0] count;
wire [3:0] st_count;

wire counting;
wire st_counting;
wire done;
wire st_done;
reg ack = 0;


initial
begin
    data <= 0;
    reset <= 1;
    
    ack <= 0;
    
    @(posedge clk); 
    @(posedge clk); 
    reset <= 0;
    data <= 1;
    @(posedge clk); 
    data <= 0;
    @(posedge clk); 
    data <= 0;
    
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    data <= 0;
    @(posedge clk); 
    data <= 1;
    
    @(posedge clk); 
    data <= 0;
    
    @(posedge clk); 
    data <= 0;
    
    @(posedge clk); 
    data <= 0;
    
    
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    data <= 1;

    @(posedge clk); 
    data <= 0;
    
    @(posedge clk); 
    data <= 1;
    
    @(posedge clk); 
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    data <= 0;
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    
    @(posedge clk); 
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    data <= 0;
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    
    
    while(!done) @(posedge clk); 
    
    @(posedge clk); 
    @(posedge clk); 
    @(posedge clk); 
    @(posedge clk); 
    @(posedge clk); 
    ack <= 1;
    
    @(posedge clk); 
    ack <= 0;
    
    
    repeat(20) @ (posedge clk);
    
    
    @(posedge clk); 
    @(posedge clk); 
    reset <= 0;
    data <= 1;
    @(posedge clk); 
    data <= 0;
    @(posedge clk); 
    data <= 0;
    
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    data <= 0;
    @(posedge clk); 
    data <= 1;
    
    @(posedge clk); 
    data <= 0;
    
    @(posedge clk); 
    data <= 0;
    
    @(posedge clk); 
    data <= 1;
    
    
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    data <= 1;

    @(posedge clk); 
    data <= 0;
    
    @(posedge clk); 
    data <= 1;
    
    @(posedge clk); 
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    data <= 0;
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    
    @(posedge clk); 
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    data <= 0;
    @(posedge clk); 
    data <= 1;
    @(posedge clk); 
    
    
    while(!done) @(posedge clk); 
    
    @(posedge clk); 
    @(posedge clk); 
    @(posedge clk); 
    @(posedge clk); 
    @(posedge clk); 
    ack <= 1;
    
    @(posedge clk); 
    ack <= 0;
    


    #60000;
    $stop;


end
    
testbench  testbench_inst 
(
    .clk    (clk),
    .reset  (reset),      // Synchronous reset
    .data   (data),
    
    .count  (count),
    .counting   (counting),
    
    .done   (done),
    .ack    (ack)
);




//top_module  top_module_inst 
//(
//    .clk    (clk),
//    .reset  (reset),      // Synchronous reset
//    .data   (data),
//    
//    .shift_ena  (st_shift_ena),
//    .counting   (st_counting),
//    
//    .done_counting  (done_counting),
//    .done   (st_done),
//    .ack    (ack)
//);

    
endmodule