`timescale 1ns / 1ps

module tb7(

    );
reg in = 0;
reg [9:0] st = 0;
wire [9:0] nst;
wire out1;
wire out2;

initial
begin
in = 1;
st = 0;
#10;
st = 1;
in = 0;
#10;
st = 2;
#10;
st = 4;
#10;
st = 8;
#10;
st = 16;
#10;
st = 32;
#10;
st = 64;
#10;
st = 128;
#10;
st = 256;
#10;
st = 512;
#10;
in = 1;
st = 1;
#10;
st = 2;
#10;
st = 4;
#10;
st = 8;
#10;
st = 16;
#10;
st = 32;
#10;
st = 64;
#10;
st = 128;
#10;
st = 256;
#10;
st = 512;

end
    
    
top_module top_inst(
.in(in),
.state(st),
. next_state(nst),
. out1(out1),
. out2(out2)
);
endmodule