`timescale 1ns / 1ps

module tb8(

    );
reg clk = 0;
reg [7:0] in = 0;
reg reset = 0;

wire done;
always #5 clk = ~clk;

initial
begin
reset <= 0;
in <= 8'h63;
@(posedge clk); 
reset <= 1;
@(posedge clk); 
reset <= 0;
@(posedge clk); 
in <= 8'h80;
@(posedge clk); 
in <= 8'haa;
@(posedge clk); 
in <= 8'h96;
@(posedge clk); 
in <= 8'hd;
@(posedge clk); 
in <= 8'h6b;
@(posedge clk); 
in <= 8'h2;
@(posedge clk); 
in <= 8'h1d;
@(posedge clk); 
in <= 8'h23;
@(posedge clk); 
in <= 8'hca;
@(posedge clk); 
in <= 8'hf2;
@(posedge clk); 
in <= 8'h41;
@(posedge clk); 
in <= 8'h78;
@(posedge clk); 
in <= 8'heb;
@(posedge clk); 
in <= 8'hc6;
@(posedge clk); 
in <= 8'hbc;
@(posedge clk); 
in <= 8'hb;
@(posedge clk); 
in <= 8'h85;
@(posedge clk); 
in <= 8'h3b;
@(posedge clk); 
in <= 8'h7e;
@(posedge clk); 
in <= 8'hf1;
@(posedge clk); 
in <= 8'h62;
@(posedge clk); 
in <= 8'h9f;



#100;
$stop;


end
    
    
top_module top_inst(
.clk(clk),
.in(in),
.reset(reset),  
. done(done)
); 
endmodule