module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 


    
    reg [2:0] st =0;
    reg [3:0] cnt = 0;
    always @ (posedge clk)
        if(reset)
        begin
			st <= 0;
    		cnt <= 0;
        end
    	else
            begin
                case(st)
                0://detect falling edge
                begin
                    cnt <= 0;

                    if(in == 0)
                        st <= 1;
                    
                end
                1: //cnt 8 numbers
                begin
                    if(cnt == 7)
                    begin
                        st <= 2;
                        cnt <= 0;
                    end
                    else
                        cnt <= cnt + 1;
                    
                end    
                2://detect high level
                begin
                    if(in)
                        st <= 3;
                    else
                        st <= 4;
                end    
                3://done
                begin
                   if(in == 0)
                      st <= 1;
                   else
                      st <= 0;
                end  
                4:
                begin
                   if(in) st <= 0;
                end
                default:st<= 0;
                endcase
            end
    
    assign done = st == 3;
endmodule