module top_module(
    input clk,
    input in,
    input reset,   
    output [7:0] out_byte,
    output done
); 
	reg odd = 0;
 
    reg [2:0] st = 0;
    reg [3:0] cnt = 0;
    always @ (posedge clk)
        if(reset)
        begin
			st <= 0;
    		cnt <= 0;
            out_byte <= 0;
            odd <= 0;
        end
    	else
            begin
                case(st)
                0://detect start bit
                begin
                    cnt <= 0;
                    odd <= 0;

                    if(in == 0)
                        st <= 1;   
                end
                1: //cnt 8 numbers
                begin
                    out_byte <= {in,out_byte[7:1]};
                    if(in) odd <= ~odd;
                    if(cnt == 7)
                    begin
                        st <= 2;
                        cnt <= 0;
                    end
                    else
                        cnt <= cnt + 1;
                end      
                2://add one parity bit
                begin
                    st <= 3;
                    if(in) odd <= ~odd;
                end    
  
                3://detect high level,stop bit
                begin
                    //if(in) odd <= ~odd;
                    
                    if(in)
                        st <= 4;
                    else
                        st <= 5;
                end    
                4://done
                begin
                   if(in == 0)
                   begin
                      st <= 1;
                       odd <= 0;
                   end
                   else
                      st <= 0;
                end  
                5:
                begin
                   if(in) st <= 0;
                end
                default:st<= 0;
                endcase
            end
    
    assign done = ((st == 4) && (odd == 1)) ;

endmodule