| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst|tx_fifo_inst|dcfifo_component|auto_generated|wrfull_eq_comp |
18 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst|tx_fifo_inst|dcfifo_component|auto_generated|rdempty_eq_comp |
18 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst|tx_fifo_inst|dcfifo_component|auto_generated|ws_dgrp|dffpipe16 |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst|tx_fifo_inst|dcfifo_component|auto_generated|ws_dgrp |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst|tx_fifo_inst|dcfifo_component|auto_generated|ws_bwp |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst|tx_fifo_inst|dcfifo_component|auto_generated|ws_brp |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst|tx_fifo_inst|dcfifo_component|auto_generated|rs_dgwp|dffpipe12 |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst|tx_fifo_inst|dcfifo_component|auto_generated|rs_dgwp |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst|tx_fifo_inst|dcfifo_component|auto_generated|fifo_ram |
30 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst|tx_fifo_inst|dcfifo_component|auto_generated|wrptr_g1p |
2 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst|tx_fifo_inst|dcfifo_component|auto_generated|rdptr_g1p |
2 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst|tx_fifo_inst|dcfifo_component|auto_generated|ws_dgrp_gray2bin |
9 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst|tx_fifo_inst|dcfifo_component|auto_generated|wrptr_g_gray2bin |
9 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst|tx_fifo_inst|dcfifo_component|auto_generated |
13 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst|tx_fifo_inst |
13 |
1 |
0 |
1 |
19 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|tx_fifo_inst |
13 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst|rx_fifo_inst|dcfifo_component|auto_generated|wrfull_eq_comp |
18 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst|rx_fifo_inst|dcfifo_component|auto_generated|rdempty_eq_comp |
18 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst|rx_fifo_inst|dcfifo_component|auto_generated|ws_dgrp|dffpipe16 |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst|rx_fifo_inst|dcfifo_component|auto_generated|ws_dgrp |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst|rx_fifo_inst|dcfifo_component|auto_generated|ws_bwp |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst|rx_fifo_inst|dcfifo_component|auto_generated|ws_brp |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst|rx_fifo_inst|dcfifo_component|auto_generated|rs_dgwp|dffpipe12 |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst|rx_fifo_inst|dcfifo_component|auto_generated|rs_dgwp |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst|rx_fifo_inst|dcfifo_component|auto_generated|fifo_ram |
30 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst|rx_fifo_inst|dcfifo_component|auto_generated|wrptr_g1p |
2 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst|rx_fifo_inst|dcfifo_component|auto_generated|rdptr_g1p |
2 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst|rx_fifo_inst|dcfifo_component|auto_generated|ws_dgrp_gray2bin |
9 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst|rx_fifo_inst|dcfifo_component|auto_generated|wrptr_g_gray2bin |
9 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst|rx_fifo_inst|dcfifo_component|auto_generated |
13 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst|rx_fifo_inst |
13 |
2 |
0 |
2 |
19 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst|rx_fifo_inst |
13 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_engine_inst |
24 |
0 |
0 |
0 |
27 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_inst|rx_more_one_inst |
4 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_inst|txd_inst |
12 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_inst|bau_rate_en_inst |
35 |
33 |
0 |
33 |
2 |
33 |
33 |
33 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_inst|uart_pll_inst|altpll_component|auto_generated |
3 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_inst|uart_pll_inst |
2 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst|uart_inst |
11 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_wrapper_inst |
13 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| user_app_inst|seg_dev_inst|scan_seg_inst |
30 |
4 |
0 |
4 |
14 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| user_app_inst|seg_dev_inst |
27 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| user_app_inst|tx_app_inst |
19 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| user_app_inst|rx_app_inst |
12 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| user_app_inst |
28 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |