# //  Questa Intel Starter FPGA Edition-64
# //  Version 2021.2 win64 Apr 14 2021
# //
# //  Copyright 1991-2021 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# do sim.tcl
# tb
# Questa Intel Starter FPGA Edition-64 vmap 2021.2 Lib Mapping Utility 2021.04 Apr 14 2021
# vmap work sim_work 
# Copying C:/intelFPGA_lite/21.1/questa_fse/win64/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# Questa Intel Starter FPGA Edition-64 vmap 2021.2 Lib Mapping Utility 2021.04 Apr 14 2021
# vmap altera_lib sim_ip 
# Modifying modelsim.ini
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:57:02 on May 25,2022
# vlog -reportprogress 300 ../../src/baud_rate_en.v ../../src/rx.v ../../src/rx_app.v ../../src/rx_more_one.v ../../src/scan_seg.v ../../src/seg_dev.v ../../src/test_uart.v ../../src/tx.v ../../src/tx_app.v ../../src/uart.v 
# -- Compiling module baud_rate_en
# -- Compiling module rx
# -- Compiling module rx_app
# -- Compiling module rx_more_one
# -- Compiling module scan_seg
# -- Compiling module seg_dev
# -- Compiling module test_uart
# -- Compiling module tx
# -- Compiling module tx_app
# -- Compiling module uart
# 
# Top level modules:
# 	rx
# 	test_uart
# End time: 12:57:02 on May 25,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:57:02 on May 25,2022
# vlog -reportprogress 300 ../../ip_cores/uart_pll.v 
# -- Compiling module uart_pll
# 
# Top level modules:
# 	uart_pll
# End time: 12:57:02 on May 25,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:57:03 on May 25,2022
# vlog -reportprogress 300 ../../test_uart/db/uart_pll_altpll.v 
# -- Compiling module uart_pll_altpll
# 
# Top level modules:
# 	uart_pll_altpll
# End time: 12:57:03 on May 25,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:57:03 on May 25,2022
# vlog -reportprogress 300 ../../tb/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 12:57:03 on May 25,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:57:03 on May 25,2022
# vlog -reportprogress 300 -work altera_lib C:\intelFPGA_lite\21.1\quartus/eda/sim_lib/altera_mf.v 
# -- Compiling module lcell
# -- Compiling module ALTERA_MF_MEMORY_INITIALIZATION
# -- Compiling module ALTERA_MF_HINT_EVALUATION
# -- Compiling module ALTERA_DEVICE_FAMILIES
# -- Compiling module dffp
# -- Compiling module pll_iobuf
# -- Compiling module stx_m_cntr
# -- Compiling module stx_n_cntr
# -- Compiling module stx_scale_cntr
# -- Compiling module MF_pll_reg
# -- Compiling module MF_stratix_pll
# -- Compiling module arm_m_cntr
# -- Compiling module arm_n_cntr
# -- Compiling module arm_scale_cntr
# -- Compiling module MF_stratixii_pll
# -- Compiling module ttn_m_cntr
# -- Compiling module ttn_n_cntr
# -- Compiling module ttn_scale_cntr
# -- Compiling module MF_stratixiii_pll
# -- Compiling module cda_m_cntr
# -- Compiling module cda_n_cntr
# -- Compiling module cda_scale_cntr
# -- Compiling module MF_cycloneiii_pll
# -- Compiling module MF_cycloneiiigl_m_cntr
# -- Compiling module MF_cycloneiiigl_n_cntr
# -- Compiling module MF_cycloneiiigl_scale_cntr
# -- Compiling module cycloneiiigl_post_divider
# -- Compiling module MF_cycloneiiigl_pll
# -- Compiling module altpll
# -- Compiling module altlvds_rx
# -- Compiling module stratix_lvds_rx
# -- Compiling module stratixgx_dpa_lvds_rx
# -- Compiling module stratixii_lvds_rx
# -- Compiling module flexible_lvds_rx
# -- Compiling module stratixiii_lvds_rx
# -- Compiling module stratixiii_lvds_rx_channel
# -- Compiling module stratixiii_lvds_rx_dpa
# -- Compiling module altlvds_tx
# -- Compiling module stratixv_local_clk_divider
# -- Compiling module stratix_tx_outclk
# -- Compiling module stratixii_tx_outclk
# -- Compiling module flexible_lvds_tx
# -- Compiling module dcfifo_dffpipe
# -- Compiling module dcfifo_fefifo
# -- Compiling module dcfifo_async
# -- Compiling module dcfifo_sync
# -- Compiling module dcfifo_low_latency
# -- Compiling module dcfifo_mixed_widths
# -- Compiling module dcfifo
# -- Compiling module altera_syncram_derived
# -- Compiling module altera_syncram_derived_forwarding_logic
# -- Compiling module altaccumulate
# -- Compiling module altmult_accum
# -- Compiling module altmult_add
# -- Compiling module altfp_mult
# -- Compiling module altsqrt
# -- Compiling module altclklock
# -- Compiling module altddio_in
# -- Compiling module altddio_out
# -- Compiling module altddio_bidir
# -- Compiling module altdpram
# -- Compiling module altsyncram
# -- Compiling module altsyncram_body
# -- Compiling module alt3pram
# -- Compiling module parallel_add
# -- Compiling module scfifo
# -- Compiling module altshift_taps
# -- Compiling module a_graycounter
# -- Compiling module altsquare
# -- Compiling module altera_std_synchronizer
# -- Compiling module altera_std_synchronizer_bundle
# -- Compiling module alt_cal
# -- Compiling module alt_cal_mm
# -- Compiling module alt_cal_c3gxb
# -- Compiling module alt_cal_sv
# -- Compiling module alt_cal_av
# -- Compiling module alt_aeq_s4
# -- Compiling module alt_eyemon
# -- Compiling module alt_dfe
# -- Compiling module signal_gen
# -- Compiling module jtag_tap_controller
# -- Compiling module dummy_hub
# -- Compiling module sld_virtual_jtag
# -- Compiling module sld_signaltap
# -- Compiling module altstratixii_oct
# -- Compiling module altparallel_flash_loader
# -- Compiling module altserial_flash_loader
# -- Compiling module alt_fault_injection
# -- Compiling module sld_virtual_jtag_basic
# -- Compiling module altsource_probe
# 
# Top level modules:
# 	lcell
# 	altpll
# 	altlvds_rx
# 	altlvds_tx
# 	dcfifo
# 	altaccumulate
# 	altmult_accum
# 	altmult_add
# 	altfp_mult
# 	altsqrt
# 	altclklock
# 	altddio_bidir
# 	altdpram
# 	alt3pram
# 	parallel_add
# 	scfifo
# 	altshift_taps
# 	a_graycounter
# 	altsquare
# 	altera_std_synchronizer_bundle
# 	alt_cal
# 	alt_cal_mm
# 	alt_cal_c3gxb
# 	alt_cal_sv
# 	alt_cal_av
# 	alt_aeq_s4
# 	alt_eyemon
# 	alt_dfe
# 	sld_virtual_jtag
# 	sld_signaltap
# 	altstratixii_oct
# 	altparallel_flash_loader
# 	altserial_flash_loader
# 	alt_fault_injection
# 	sld_virtual_jtag_basic
# 	altsource_probe
# End time: 12:57:03 on May 25,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
