# Reading D:/FPGA/software/quartus/quartus/modelsim_ase/tcl/vsim/pref.tcl
# do uart_app_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap work rtl_work 
# Copying D:/FPGA/software/quartus/quartus/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/src {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/uart.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/uart.v 
# -- Compiling module uart
# 
# Top level modules:
# 	uart
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/src {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/tx.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/tx.v 
# -- Compiling module tx
# 
# Top level modules:
# 	tx
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/src {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/uart_app.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/uart_app.v 
# -- Compiling module uart_app
# 
# Top level modules:
# 	uart_app
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/src {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/user_app.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/user_app.v 
# -- Compiling module user_app
# 
# Top level modules:
# 	user_app
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/src {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/rx_more_one.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/rx_more_one.v 
# -- Compiling module rx_more_one
# 
# Top level modules:
# 	rx_more_one
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/src {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/baud_rate_en.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/baud_rate_en.v 
# -- Compiling module baud_rate_en
# 
# Top level modules:
# 	baud_rate_en
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/src {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/scan_seg.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/scan_seg.v 
# -- Compiling module scan_seg
# 
# Top level modules:
# 	scan_seg
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/src {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/rx_app.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/rx_app.v 
# -- Compiling module rx_app
# 
# Top level modules:
# 	rx_app
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/src {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/seg_dev.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/seg_dev.v 
# -- Compiling module seg_dev
# 
# Top level modules:
# 	seg_dev
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/src {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/tx_app.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/tx_app.v 
# -- Compiling module tx_app
# 
# Top level modules:
# 	tx_app
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/src {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/uart_engine.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/uart_engine.v 
# -- Compiling module uart_engine
# 
# Top level modules:
# 	uart_engine
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/src {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/uart_wrapper.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/uart_wrapper.v 
# -- Compiling module uart_wrapper
# 
# Top level modules:
# 	uart_wrapper
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/ip_cores {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/ip_cores/uart_pll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/ip_cores" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/ip_cores/uart_pll.v 
# -- Compiling module uart_pll
# 
# Top level modules:
# 	uart_pll
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/ip_cores {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/ip_cores/fifo.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/ip_cores" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/ip_cores/fifo.v 
# -- Compiling module fifo
# 
# Top level modules:
# 	fifo
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/uart_app {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/rx_fifo.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/rx_fifo.v 
# -- Compiling module rx_fifo
# 
# Top level modules:
# 	rx_fifo
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/uart_app {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/tx_fifo.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:45 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/tx_fifo.v 
# -- Compiling module tx_fifo
# 
# Top level modules:
# 	tx_fifo
# End time: 16:53:45 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/uart_app/db {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/db/uart_pll_altpll.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:46 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/db" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/db/uart_pll_altpll.v 
# -- Compiling module uart_pll_altpll
# 
# Top level modules:
# 	uart_pll_altpll
# End time: 16:53:46 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+C:/Users/24836/Desktop/program/uart/uart_fifo\ _check/uart_fifo/uart_app/../tb {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/../tb/tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:53:46 on Jun 14,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/../tb" C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/../tb/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 16:53:46 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc"  tb
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" tb 
# Start time: 16:53:46 on Jun 14,2022
# Loading work.tb
# Loading work.uart_app
# Loading work.user_app
# Loading work.rx_app
# Loading work.tx_app
# Loading work.seg_dev
# Loading work.scan_seg
# Loading work.uart_wrapper
# Loading work.uart
# Loading work.uart_pll
# Loading altera_mf_ver.altpll
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading altera_mf_ver.pll_iobuf
# Loading work.baud_rate_en
# Loading work.tx
# Loading work.rx_more_one
# Loading work.uart_engine
# Loading work.rx_fifo
# Loading work.fifo
# Loading altera_mf_ver.dcfifo
# Loading altera_mf_ver.dcfifo_mixed_widths
# Loading altera_mf_ver.dcfifo_low_latency
# Loading altera_mf_ver.ALTERA_MF_HINT_EVALUATION
# Loading altera_mf_ver.dcfifo_dffpipe
# Loading work.tx_fifo
# Loading altera_mf_ver.MF_cycloneiii_pll
# Loading altera_mf_ver.cda_m_cntr
# Loading altera_mf_ver.cda_n_cntr
# Loading altera_mf_ver.cda_scale_cntr
# Loading altera_mf_ver.dcfifo_async
# Loading altera_mf_ver.dcfifo_fefifo
# ** Warning: (vsim-3017) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Too few port connections. Expected 14, found 13.
#    Time: 0 ps  Iteration: 0  Instance: /tb/uart_app_inst/uart_wrapper_inst/uart_engine_inst/rx_fifo_inst/rx_fifo_inst/dcfifo_component/DCFIFO_MW File: /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v
# ** Warning: (vsim-3722) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Missing connection for port 'eccstatus'.
# ** Warning: (vsim-3017) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Too few port connections. Expected 14, found 13.
#    Time: 0 ps  Iteration: 0  Instance: /tb/uart_app_inst/uart_wrapper_inst/uart_engine_inst/tx_fifo_inst/tx_fifo_inst/dcfifo_component/DCFIFO_MW File: /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v
# ** Warning: (vsim-3722) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Missing connection for port 'eccstatus'.
# 
# add wave *
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
#           File in use by: 24836  Hostname: LAPTOP-QTGTPOO6  ProcessID: 20112
#           Attempting to use alternate WLF file "./wlft7qgqne".
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
#           Using alternate file: ./wlft7qgqne
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 80000  Instance: tb.uart_app_inst.uart_wrapper_inst.uart_inst.uart_pll_inst.altpll_component.cycloneiii_pll.pll3
add wave -position end sim:/tb/uart_app_inst/user_app_inst/rx_app_inst/*
# ** Note: $stop    : C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/../tb/tb.v(25)
#    Time: 2300 us  Iteration: 0  Instance: /tb
# Break in Module tb at C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/../tb/tb.v line 25
restart
# ** Warning: (vsim-3017) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Too few port connections. Expected 14, found 13.
#    Time: 0 ps  Iteration: 0  Instance: /tb/uart_app_inst/uart_wrapper_inst/uart_engine_inst/rx_fifo_inst/rx_fifo_inst/dcfifo_component/DCFIFO_MW File: /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v
# ** Warning: (vsim-3722) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Missing connection for port 'eccstatus'.
# ** Warning: (vsim-3017) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Too few port connections. Expected 14, found 13.
#    Time: 0 ps  Iteration: 0  Instance: /tb/uart_app_inst/uart_wrapper_inst/uart_engine_inst/tx_fifo_inst/tx_fifo_inst/dcfifo_component/DCFIFO_MW File: /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v
# ** Warning: (vsim-3722) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Missing connection for port 'eccstatus'.
run -all
# GetModuleFileName: Ҳָģ顣
# 
# 
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 80000  Instance: tb.uart_app_inst.uart_wrapper_inst.uart_inst.uart_pll_inst.altpll_component.cycloneiii_pll.pll3
# ** Note: $stop    : C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/../tb/tb.v(25)
#    Time: 2300 us  Iteration: 0  Instance: /tb
# Break in Module tb at C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/../tb/tb.v line 25
vlog -reportprogress 300 -work work {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/rx_app.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 16:57:15 on Jun 14,2022
# vlog -reportprogress 300 -work work C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/src/rx_app.v 
# -- Compiling module rx_app
# 
# Top level modules:
# 	rx_app
# End time: 16:57:15 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.rx_app
# ** Warning: (vsim-3017) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Too few port connections. Expected 14, found 13.
#    Time: 0 ps  Iteration: 0  Instance: /tb/uart_app_inst/uart_wrapper_inst/uart_engine_inst/rx_fifo_inst/rx_fifo_inst/dcfifo_component/DCFIFO_MW File: /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v
# ** Warning: (vsim-3722) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Missing connection for port 'eccstatus'.
# ** Warning: (vsim-3017) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Too few port connections. Expected 14, found 13.
#    Time: 0 ps  Iteration: 0  Instance: /tb/uart_app_inst/uart_wrapper_inst/uart_engine_inst/tx_fifo_inst/tx_fifo_inst/dcfifo_component/DCFIFO_MW File: /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v
# ** Warning: (vsim-3722) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Missing connection for port 'eccstatus'.
run -all
# GetModuleFileName: Ҳָģ顣
# 
# 
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 80000  Instance: tb.uart_app_inst.uart_wrapper_inst.uart_inst.uart_pll_inst.altpll_component.cycloneiii_pll.pll3
# ** Note: $stop    : C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/../tb/tb.v(25)
#    Time: 2300 us  Iteration: 0  Instance: /tb
# Break in Module tb at C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/uart_app/../tb/tb.v line 25
vlog -reportprogress 300 -work work {C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/tb/tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 17:03:27 on Jun 14,2022
# vlog -reportprogress 300 -work work C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/tb/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 17:03:27 on Jun 14,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.tb
# ** Warning: (vsim-3017) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Too few port connections. Expected 14, found 13.
#    Time: 0 ps  Iteration: 0  Instance: /tb/uart_app_inst/uart_wrapper_inst/uart_engine_inst/rx_fifo_inst/rx_fifo_inst/dcfifo_component/DCFIFO_MW File: /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v
# ** Warning: (vsim-3722) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Missing connection for port 'eccstatus'.
# ** Warning: (vsim-3017) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Too few port connections. Expected 14, found 13.
#    Time: 0 ps  Iteration: 0  Instance: /tb/uart_app_inst/uart_wrapper_inst/uart_engine_inst/tx_fifo_inst/tx_fifo_inst/dcfifo_component/DCFIFO_MW File: /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v
# ** Warning: (vsim-3722) /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(31790): [TFMPC] - Missing connection for port 'eccstatus'.
run -all
# GetModuleFileName: Ҳָģ顣
# 
# 
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 80000  Instance: tb.uart_app_inst.uart_wrapper_inst.uart_inst.uart_pll_inst.altpll_component.cycloneiii_pll.pll3
# ** Note: $stop    : C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/tb/tb.v(25)
#    Time: 2300 us  Iteration: 0  Instance: /tb
# Break in Module tb at C:/Users/24836/Desktop/program/uart/uart_fifo _check/uart_fifo/tb/tb.v line 25
# End time: 18:33:07 on Jun 14,2022, Elapsed time: 1:39:21
# Errors: 0, Warnings: 18
