
State Machine - |uart_app|uart_wrapper:uart_wrapper_inst|uart_engine:uart_engine_inst|tx_fifo:tx_fifo_inst|tx_rd_st
Name tx_rd_st.011 tx_rd_st.010 tx_rd_st.001 tx_rd_st.000 
tx_rd_st.000 0 0 0 0 
tx_rd_st.001 0 0 1 1 
tx_rd_st.010 0 1 0 1 
tx_rd_st.011 1 0 0 1 

State Machine - |uart_app|uart_wrapper:uart_wrapper_inst|uart_engine:uart_engine_inst|rx_fifo:rx_fifo_inst|rx_wr_st
Name rx_wr_st.001 
rx_wr_st.000 0 
rx_wr_st.001 1 

State Machine - |uart_app|uart_wrapper:uart_wrapper_inst|uart:uart_inst|rx_more_one:rx_more_one_inst|sample_st_cs
Name sample_st_cs.STOP2_BIT sample_st_cs.STOP1_BIT sample_st_cs.PAR_BIT sample_st_cs.EIGTH_BIT sample_st_cs.SEVN_BIT sample_st_cs.SIX_BIT sample_st_cs.FIF_BIT sample_st_cs.FOUTH_BIT sample_st_cs.THIRD_BIT sample_st_cs.SEC_BIT sample_st_cs.FIRST_BIT sample_st_cs.START sample_st_cs.IDLE1 sample_st_cs.IDLE0 
sample_st_cs.IDLE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
sample_st_cs.IDLE1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
sample_st_cs.START 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
sample_st_cs.FIRST_BIT 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
sample_st_cs.SEC_BIT 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
sample_st_cs.THIRD_BIT 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
sample_st_cs.FOUTH_BIT 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
sample_st_cs.FIF_BIT 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
sample_st_cs.SIX_BIT 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
sample_st_cs.SEVN_BIT 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
sample_st_cs.EIGTH_BIT 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
sample_st_cs.PAR_BIT 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
sample_st_cs.STOP1_BIT 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
sample_st_cs.STOP2_BIT 1 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |uart_app|uart_wrapper:uart_wrapper_inst|uart:uart_inst|tx:tx_inst|tx_st
Name tx_st.STOP2_BIT tx_st.STOP1_BIT tx_st.PAR_BIT tx_st.EIGTH_BIT tx_st.SEVN_BIT tx_st.SIX_BIT tx_st.FIF_BIT tx_st.FOUTH_BIT tx_st.THIRD_BIT tx_st.SEC_BIT tx_st.FIRST_BIT tx_st.START tx_st.0000 
tx_st.0000 0 0 0 0 0 0 0 0 0 0 0 0 0 
tx_st.START 0 0 0 0 0 0 0 0 0 0 0 1 1 
tx_st.FIRST_BIT 0 0 0 0 0 0 0 0 0 0 1 0 1 
tx_st.SEC_BIT 0 0 0 0 0 0 0 0 0 1 0 0 1 
tx_st.THIRD_BIT 0 0 0 0 0 0 0 0 1 0 0 0 1 
tx_st.FOUTH_BIT 0 0 0 0 0 0 0 1 0 0 0 0 1 
tx_st.FIF_BIT 0 0 0 0 0 0 1 0 0 0 0 0 1 
tx_st.SIX_BIT 0 0 0 0 0 1 0 0 0 0 0 0 1 
tx_st.SEVN_BIT 0 0 0 0 1 0 0 0 0 0 0 0 1 
tx_st.EIGTH_BIT 0 0 0 1 0 0 0 0 0 0 0 0 1 
tx_st.PAR_BIT 0 0 1 0 0 0 0 0 0 0 0 0 1 
tx_st.STOP1_BIT 0 1 0 0 0 0 0 0 0 0 0 0 1 
tx_st.STOP2_BIT 1 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |uart_app|cpu_test_if:cpu_test_if_inst|wr_st
Name wr_st.0011 wr_st.0010 wr_st.0001 wr_st.0000 
wr_st.0000 0 0 0 0 
wr_st.0001 0 0 1 1 
wr_st.0010 0 1 0 1 
wr_st.0011 1 0 0 1 

State Machine - |uart_app|user_app:user_app_inst|tx_app:tx_app_inst|wr_st
Name wr_st.0011 wr_st.0010 wr_st.0001 wr_st.0000 
wr_st.0000 0 0 0 0 
wr_st.0001 0 0 1 1 
wr_st.0010 0 1 0 1 
wr_st.0011 1 0 0 1 

State Machine - |uart_app|user_app:user_app_inst|rx_app:rx_app_inst|chk_st
Name chk_st.10101 chk_st.10100 chk_st.01111 chk_st.01110 chk_st.01101 chk_st.01100 chk_st.01000 chk_st.00111 chk_st.00110 chk_st.00101 chk_st.00100 chk_st.00011 chk_st.00010 chk_st.00001 chk_st.00000 
chk_st.00000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
chk_st.00001 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
chk_st.00010 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
chk_st.00011 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
chk_st.00100 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
chk_st.00101 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
chk_st.00110 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
chk_st.00111 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
chk_st.01000 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
chk_st.01100 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
chk_st.01101 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
chk_st.01110 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
chk_st.01111 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
chk_st.10100 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 
chk_st.10101 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |uart_app|user_app:user_app_inst|rx_app:rx_app_inst|rd_st
Name rd_st.0101 rd_st.0100 rd_st.0011 rd_st.0010 rd_st.0001 rd_st.0000 
rd_st.0000 0 0 0 0 0 0 
rd_st.0001 0 0 0 0 1 1 
rd_st.0010 0 0 0 1 0 1 
rd_st.0011 0 0 1 0 0 1 
rd_st.0100 0 1 0 0 0 1 
rd_st.0101 1 0 0 0 0 1 
